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1 features ? high-performance, low-power avr ? 8-bit microcontroller ? advanced risc architecture ? 133 powerful instructions ? most single clock cycl e execution ? 32 x 8 general purpose working registers + periphe ral control registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non volatile program and data memories ? 32k/64k/128k bytes of in-system reprogrammable fla sh (at90can32/64/128) ? endurance: 10,000 write/erase cycles ? optional boot code section with independent lock b its ? selectable boot size: 1k bytes, 2k bytes, 4k bytes or 8k bytes ? in-system programming by on-chip boot program (can , uart, ...) ? true read-while-write operation ? 1k/2k/4k bytes eeprom (endurance: 100,000 write/erase cycles ) (at90can32/64/128) ? 2k/4k/4k bytes internal sram (at90can32/64/128) ? up to 64k bytes optional external memory space ? programming lock for software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag s tandard ? programming flash (hardware isp), eeprom, lock & f use bits ? extensive on-chip debug support ? can controller 2.0a & 2.0b - iso 16845 certified (1) ? 15 full message objects with separate identifier t ags and masks ? transmit, receive, automatic reply and frame buffe r receive modes ? 1mbits/s maximum transfer rate at 8 mhz ? time stamping, ttc & listening mode (spying or aut obaud) ? peripheral features ? programmable watchdog timer with on-chip oscillato r ? 8-bit synchronous timer/counter-0 ? 10-bit prescaler ? external event counter ? output compare or 8-bit pwm output ? 8-bit asynchronous timer/counter-2 ? 10-bit prescaler ? external event counter ? output compare or 8-bit pwm output ? 32khz oscillator for rtc operation ? dual 16-bit synchronous timer/counters-1 & 3 ? 10-bit prescaler ? input capture with noise canceler ? external event counter ? 3-output compare or 16-bit pwm output ? output compare modulation ? 8-channel, 10-bit sar adc ? 8 single-ended channels ? 7 differential channels ? 2 differential channels with programmable gain at 1x, 10x, or 200x ? on-chip analog comparator ? byte-oriented two-wire serial interface ? dual programmable serial usart ? master/slave spi serial interface ? programming flash (hardware isp) ? special microcontroller features ? power-on reset and programmable brown-out detectio n ? internal calibrated rc oscillator ? 8 external interrupt sources ? 5 sleep modes: idle, adc noise reduction, power-sa ve, power-down & standby ? software selectable clock frequency ? global pull-up disable ? i/o and packages ? 53 programmable i/o lines ? 64-lead tqfp and 64-lead qfn ? operating voltages: 2.7 - 5.5v ? operating temperature: automotive (-40c to +125c) ? maximum frequency: 8 mhz at 2.7v, 16 mhz at 4.5v note: 1. see details on section 19.4.3 on page 241 . rev. 7682c?auto?04/08 8-bit microcontroller with 32k/64k/128k bytes of isp flash and can controller at90can32 at90can64 at90can128 automotive
2 7682c?auto?04/08 at90can32/64/128 1. description 1.1 comparison between at90can32, at90can64 and at90 can128 at90can32, at90can64 and at90can128 are all hardwar e and software compatible with each other, the only difference is the memory size. 1.2 part description the at90can32/64/128 is a low-power cmos 8-bit micr ocontroller based on the avr enhanced risc architecture. by executing powerful i nstructions in a single clock cycle, the at90can32/64/128 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus proce ssing speed. the avr core combines a rich instruction set with 3 2 general purpose working registers. all 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional cisc microcontrollers. the at90can32/64/128 provides the following feature s: 32k/64k/128k bytes of in-system pro- grammable flash with read-while-write capabilities, 1k/2k/4k bytes eeprom, 2k/4k/4k bytes sram, 53 general purpose i/o lines, 32 genera l purpose working registers, a can con- troller, real time counter (rtc), four flexible tim er/counters with compare modes and pwm, 2 usarts, a byte oriented two-wire serial interface, an 8-channel 10-bit adc with optional differ- ential input stage with programmable gain, a progra mmable watchdog timer with internal oscillator, an spi serial port, ieee std. 1149.1 co mpliant jtag test interface, also used for accessing the on-chip debug system and programming and five software selectable power sav- ing modes. the idle mode stops the cpu while allowing the sram , timer/counters, spi/can ports and interrupt system to continue functioning. the power -down mode saves the register contents but freezes the oscillator, disabling all other chip fu nctions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer c ontinues to run, allowing the user to main- tain a timer base while the rest of the device is s leeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous tim er and adc, to minimize switching noise during adc conversions. in standby mode, the crysta l/resonator oscillator is running while the rest of the device is sleeping. this allows very fa st start-up combined with low power consumption. the device is manufactured using atmel?s high-densi ty nonvolatile memory technology. the on- chip isp flash allows the program memory to be repr ogrammed in-system through an spi serial interface, by a conventional nonvolatile memory pro grammer, or by an on-chip boot program running on the avr core. the boot program can use a ny interface to download the application program in the application flash memory. software i n the boot flash section will continue to run while the application flash section is updated, pro viding true read-while-write operation. by table 1-1. memory size summary device flash eeprom ram at90can32 32k bytes 1k byte 2k bytes at90can64 64k bytes 2k bytes 4k bytes at90can128 128k bytes 4k byte 4k bytes
3 7682c?auto?04/08 at90can32/64/128 combining an 8-bit risc cpu with in-system self-pro grammable flash on a monolithic chip, the atmel at90can32/64/128 is a powerful microcontr oller that provides a highly flexible and cost effective solution to many embedded control ap plications. the at90can32/64/128 avr is supported with a full s uite of program and system development tools including: c compilers, macro assemblers, pro gram debugger/simulators, in-circuit emula- tors, and evaluation kits. 1.3 disclaimer typical values contained in this datasheet are base d on simulations and characterization of other avr microcontrollers manufactured on the same process technology. min and max values will be available after the device is characterized . 1.4 automotive quality grade the at90can32/64/128 have been developed and manufa ctured according to the most strin- gent requirements of the international standard iso -ts-16949 grade 1. this data sheet contains limit values extracted from the results of extensiv e characterization (temperature and voltage). the quality and reliability of the at90can32/64/128 have been verified during regular product qualification as per aec-q100. as indicated in the ordering information paragraph, the products are available in three different temperature grades, but with equivalent quality and reliability objectives. different temperature identifiers have been defined as listed in table 1-2 . table 1-2. temperature grade identification for automotive pro ducts temperature temperature identifier comments -40 ; +85 t similar to industrial temperature grade b ut with automotive quality -40 ; +105 t1 reduced automotive temperature range -40 ; +125 z full automotivetemperature range
4 7682c?auto?04/08 at90can32/64/128 1.5 block diagram figure 1-1. block diagram program counter stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta da ta register portd interrupt unit eeprom spi usart0 status register z y x alu portb drivers porte drivers por t a drivers portf drivers portd drivers portc drivers pb7 - pb0 pe7 - pe0 pa7 - pa0 pf7 - pf0 reset vcc agnd gnd aref xtal1 xtal2 control lines + - analog comp arator pc7 - pc0 internal oscillator watchdog timer 8-bit data bus avcc usart1 timing and control oscillator oscillator calib. osc data dir. reg. portc data register portc on-chip debug jtag tap programming logic boundary- scan data dir. reg. portf data register portf adc por - bod reset pd7 - pd0 data dir. reg. portg da ta reg. portg portg drivers pg4 - pg0 two-wire serial interface can controller
5 7682c?auto?04/08 at90can32/64/128 1.6 pin configurations figure 1-2. pinout at90can32/64/128 - tqfp pc0 (a8) vcc gnd pf0 (adc0) pf7 (adc7 / tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4 / tck) pf5 (adc5 / tms) pf6 (adc6 / tdo) aref gnd avcc 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 49 32 31 30 (rxd0 / pdi) pe0 (txd0 / pdo) pe1 (xck0 / ain0) pe2 (oc3a / ain1) pe3 (oc3b / int4) pe4 (oc3c / int5) pe5 (t3 / int6) pe6 (icp3 / int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc2a) pb4 (oc0a / oc1c) pb7 (tosc2 ) pg3 (oc1b) pb6 (tosc1 ) pg4 (oc1a) pb5 pc1 (a9) (t0) pd7 pc2 (a10) pc3 (a11) pc4 (a12) pc5 (a13) pc6 (a14) pc7 (a15 / clko) pa7 (ad7) pg2 (ale) pa6 (ad6) pa5 (ad5) pa4 (ad4) pa3 (ad3) pa0 (ad0) pa1 (ad1) pa2 (ad2) (rxcan / t1) pd6 (txcan / xck1) pd5 (icp1) pd4 (txd1 / int3) pd3 (rxd1 / int2) pd2 (sda / int1) pd1 (scl / int0) pd0 xtal1 xtal2 reset gnd vcc pg1 (rd) pg0 (wr) 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 (2) (2) nc = do not connect (may be used in future devices) (1) timer2 oscillator (2) nc (1) (64-lead tqfp top view) index corner
6 7682c?auto?04/08 at90can32/64/128 figure 1-3. pinout at90can32/64/128 - qfn note: the large center pad underneath the qfn packag e is made of metal and internally connected to gnd. it should be soldered or glued to the board to ensure good mechanical stability. if the center pad is left unconnected, the package might loosen f rom the board. 1.7 pin descriptions 1.7.1 vcc digital supply voltage. 1.7.2 gnd ground. nc = do not connect (may be used in future devices) (1) timer2 oscillator (2) pc0 (a8) vcc gnd pf0 (adc0) pf7 (adc7 / tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4 / tck) pf5 (adc5 / tms) pf6 (adc6 / tdo) aref gnd avcc (rxd0 / pdi) pe0 (txd0 / pdo) pe1 (xck0 / ain0) pe2 (oc3a / ain1) pe3 (oc3b / int4) pe4 (oc3c / int5) pe5 (t3 / int6) pe6 (icp3 / int7) pe7 (ss) pb0 (sck) pb1 (mosi) pb2 (miso) pb3 (oc2a) pb4 (oc0a / oc1c) pb7 (tosc2 ) pg3 (oc1b) pb6 (tosc1 ) pg4 (oc1a) pb5 pc1 (a9) (t0) pd7 pc2 (a10) pc3 (a11) pc4 (a12) pc5 (a13) pc6 (a14) pc7 (a15 / clko) pa7 (ad7) pg2 (ale) pa6 (ad6) pa5 (ad5) pa4 (ad4) pa3 (ad3) pa0 (ad0) pa1 (ad1) pa2 (ad2) (rxcan / t1) pd6 (txcan / xck1) pd5 (icp1) pd4 (txd1 / int3) pd3 (rxd1 / int2) pd2 (sda / int1) pd1 (scl / int0) pd0 xtal1 xtal2 reset gnd vcc pg1 (rd) pg0 (wr) 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 33 15 47 46 48 45 44 43 42 41 40 39 38 37 36 35 34 (2) (2) nc (1) 17 18 20 19 21 22 23 24 25 26 27 29 28 32 31 30 52 51 50 49 64 63 62 53 61 60 59 58 57 56 55 54 (64-lead qfn top view) index corner
7 7682c?auto?04/08 at90can32/64/128 1.7.3 port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). th e port a output buffers have symmetrical drive charac teristics with both high sink and source capability. as inputs, port a pins that are externa lly pulled low will source current if the pull-up resistors are activated. the port a pins are tri-st ated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the at90can32/64/128 as listed on page 74 . 1.7.4 port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). th e port b output buffers have symmetrical drive charac teristics with both high sink and source capability. as inputs, port b pins that are externa lly pulled low will source current if the pull-up resistors are activated. the port b pins are tri-st ated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the at90can32/64/128 as listed on page 76 . 1.7.5 port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). th e port c output buffers have symmetrical drive charac teristics with both high sink and source capability. as inputs, port c pins that are externa lly pulled low will source current if the pull-up resistors are activated. the port c pins are tri-st ated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special feature s of the at90can32/64/128 as listed on page 78 . 1.7.6 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). th e port d output buffers have symmetrical drive charac teristics with both high sink and source capability. as inputs, port d pins that are externa lly pulled low will source current if the pull-up resistors are activated. the port d pins are tri-st ated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the at90can32/64/128 as listed on page 80 . 1.7.7 port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with int ernal pull-up resistors (selected for each bit). th e port e output buffers have symmetrical drive charac teristics with both high sink and source capability. as inputs, port e pins that are externa lly pulled low will source current if the pull-up resistors are activated. the port e pins are tri-st ated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the at90can32/64/128 as listed on page 83 . 1.7.8 port f (pf7..pf0) port f serves as the analog inputs to the a/d conve rter.
8 7682c?auto?04/08 at90can32/64/128 port f also serves as an 8-bit bi-directional i/o p ort, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected fo r each bit). the port f output buffers have sym- metrical drive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. port f also serves the functions of the jtag interf ace. if the jtag interface is enabled, the pull- up resistors on pins pf7(tdi), pf5(tms), and pf4(tc k) will be activated even if a reset occurs. 1.7.9 port g (pg4..pg0) port g is a 5-bit i/o port with internal pull-up re sistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are externally pulled low will source current if the pull-up resistors are activated. the port g pins are tri-stated when a re set condition becomes active, even if the clock is not running. port g also serves the functions of various special features of the at90can32/64/128 as listed on page 88 . 1.7.10 reset reset input. a low level on this pin for longer tha n the minimum pulse length will generate a reset. the minimum pulse length is given in charact eristics. shorter pulses are not guaranteed to generate a reset. the i/o ports of the avr are i mmediately reset to their initial state even if the clock is not running. the clock is needed to re set the rest of the at90can32/64/128. 1.7.11 xtal1 input to the inverting oscillator amplifier and inp ut to the internal clock operating circuit. 1.7.12 xtal2 output from the inverting oscillator amplifier. 1.7.13 avcc avcc is the supply voltage pin for the a/d converte r on port f. it should be externally con- nected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 1.7.14 aref this is the analog reference pin for the a/d conver ter. 2. about code examples this documentation contains simple code examples th at briefly show how to use various parts of the device. these code examples assume that the par t specific header file is included before compilation. be aware that not all c compiler vendo rs include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details.
9 7682c?auto?04/08 at90can32/64/128 3. avr cpu core 3.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu mus t therefore be able to access memories, perform calculations, control peripherals, and hand le interrupts. 3.2 architectural overview figure 3-1. block diagram of the avr architecture in order to maximize performance and parallelism, t he avr uses a harvard architecture ? with separate memories and buses for program and data. i nstructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this c oncept enables instructions to be executed in every clock cycle. the program memory is in-syst em reprogrammable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n
10 7682c?auto?04/08 at90can32/64/128 the fast-access register file contains 32 x 8-bit g eneral purpose working registers with a single clock cycle access time. this allows single-cycle a rithmetic logic unit (alu) operation. in a typ- ical alu operation, two operands are output from th e register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calcu lations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations be tween registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect inf ormation about the result of the operation. program flow is provided by conditional and uncondi tional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sectio ns, the boot program section and the application program section. both sections have ded icated lock bits for write and read/write protection. the spm (store program memory) instruct ion that writes into the application flash memory section must reside in the boot program sect ion. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the ge neral data sram, and consequently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subr outines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o sp ace. the data sram can easily be accessed through the five different addressing modes support ed in the avr architecture. the memory spaces in the avr architecture are all l inear and regular memory maps. a flexible interrupt module has its control registe rs in the i/o space with an additional global interrupt enable bit in the status register. all in terrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priorit y in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the h igher is the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register fil e, 0x20 - 0x5f. in addition, the at90can32/64/128 has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 3.3 alu ? arithmetic logic unit the high-performance avr alu operates in direct con nection with all the 32 general purpose working registers. within a single clock cycle, ari thmetic operations between general purpose registers or between a register and an immediate ar e executed. the alu operations are divided into three main categories ? arithmetic, logical, a nd bit-functions. some implementations of the architecture also provide a powerful multiplier sup porting both signed/unsigned multiplication and fractional format. see the ?instruction set summary? section for a detailed description.
11 7682c?auto?04/08 at90can32/64/128 3.4 status register the status register contains information about the result of the most recently executed arith- metic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status regist er is updated after all alu operations, as specified in the instruction set reference. this wi ll in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored whe n entering an interrupt routine and restored when returning from an interrupt. this must be hand led by software. the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set to enab led the interrupts. the individual interrupt enable control is then performed in separate contro l registers. if the global interrupt enable register is cleared, none of the interrupts are ena bled independent of the individual interrupt enable settings. the i-bit is cleared by hardware a fter an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupt s. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in som e arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set descrip tion? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s compleme nt overflow flag v. see the ?instruction set descripti on? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the ?instruction set description? for detailed informat ion. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed informat ion. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arith metic or logic operation. see the ?instruction set description? for detailed information. bit 7 6 5 4 3 2 1 0 i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
12 7682c?auto?04/08 at90can32/64/128 ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for detailed information. 3.5 general purpose register file the register file is optimized for the avr enhanced risc instruction set. in order to achieve the required performance and flexibility, the follo wing input/output schemes are supported by the register file: ? one 8-bit output operand and one 8-bit result inpu t ? two 8-bit output operands and one 8-bit result inp ut ? two 8-bit output operands and one 16-bit result in put ? one 16-bit output operand and one 16-bit result in put figure 3-2 shows the structure of the 32 general purpose work ing registers in the cpu. figure 3-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 3-2 , each register is also assigned a data memory addr ess, mapping them directly into the first 32 locations of the user da ta space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers ca n be set to index any register in the file. 3.5.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect add ressing of the data space. the three indirect address registers x, y, and z are defined as descri bed in figure 3-3 . 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte
13 7682c?auto?04/08 at90can32/64/128 figure 3-3. the x-, y-, and z-registers in the different addressing modes these address reg isters have functions as fixed displacement, automatic increment, and automatic decrement (see t he instruction set reference for details). 3.5.2 extended z-pointer register for elpm/spm ? ram pz ? bits 7..1 ? res: reserved bits these bits are reserved for future use and will alw ays read as zero. for compatibility with future devices, be sure to write to write them to zero. ? bit 0 ? rampz0: extended ram page z-pointer the rampz register is normally used to select which 64k ram page is accessed by the z- pointer. as the at90can32/64/128 does not support m ore than 64k of sram memory, this reg- ister is used only to select which page in the prog ram memory is accessed when the elpm/spm instruction is used. the different settings of the rampz0 bit have the following effects: ? at90can32 and at90can64: rampz0 exists as register bit but it is not used for program memory addressing. ? at90can128: rampz0 exists as register bit and it i s used for program memory addressing. figure 3-4. the z-pointer used by elpm and spm note: lpm (different of elpm) is never affected by t he rampz setting. 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) bit 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? rampz0 rampz read/write r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 rampz0 = 0: program memory address 0x0000 - 0x7fff ( lower 64k bytes) is accessed by elpm/spm rampz0 = 1: program memory address 0x8000 - 0xffff ( higher 64k bytes) is accessed by elpm/spm rampz zh zl 7 bit (individually) 0 7 0 7 0 23 bit (z-pointer) 16 15 8 7 0
14 7682c?auto?04/08 at90can32/64/128 3.6 stack pointer the stack is mainly used for storing temporary data , for storing local variables and for storing return addresses after interrupts and subroutine ca lls. the stack pointer register always points to the top of the stack. note that the stack is imp lemented as growing from higher memory loca- tions to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack are a where the subroutine and interrupt stacks are located. this stack space in the data sr am must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0xff. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the st ack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine r et or return from interrupt reti. the avr stack pointer is implemented as two 8-bit r egisters in the i/o space. the number of bits actually used is implementation dependent. not e that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 3.7 instruction execution timing this section describes the general access timing co ncepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 3-5 shows the parallel instruction fetches and instruc tion executions enabled by the har- vard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the correspondi ng unique results for functions per cost, functions per clocks, and functions per power-unit. figure 3-5. the parallel instruction fetches and instruction ex ecutions bit 15 14 13 12 11 10 9 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 7 6 5 4 3 2 1 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu
15 7682c?auto?04/08 at90can32/64/128 figure 3-6 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 3-6. single cycle alu operation 3.8 reset and interrupt handling the avr provides several different interrupt source s. these interrupts and the separate reset vector each have a separate program vector in the p rogram memory space. all interrupts are assigned individual enable bits which must be writt en logic one together with the global interrupt enable bit in the status register in order to enabl e the interrupt. depending on the program counter value, interrupts may be automatically disa bled when boot lock bits blb02 or blb12 are programmed. this feature improves software secu rity. see the section ?memory program- ming? on page 335 for details. the lowest addresses in the program memory space ar e by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 60 . the list also determines the priority levels of the different int errupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control register (mcucr). refer to ?interrupts? on page 60 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse, see ?boot loader support ? read-while-write self-progra mming? on page 320 . 3.8.1 interrupt behavior when an interrupt occurs, the global interrupt enab le i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is execu ted. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program c ounter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, and hardware clears the corresponding inter- rupt flag. interrupt flags can also be cleared by w riting a logic one to the flag bit position(s) to b e cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt co nditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be execu ted by order of priority. total execution t ime register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu
16 7682c?auto?04/08 at90can32/64/128 the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the interrupt will not be tri ggered. when the avr exits from an interrupt, it will alway s return to the main program and execute one more instruction before any pending interrupt is se rved. note that the status register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupt s, the interrupts will be immediately disabled. no interrupt will be executed after the cli instruc tion, even if it occurs simultaneously with the cli instruction. the following example shows how th is can be used to avoid interrupts during the timed eeprom write sequence. when using the sei instruction to enable interrupts , the instruction following sei will be exe- cuted before any pending interrupts, as shown in th is example. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eemwe ; start eeprom write sbi eecr, eewe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 17 7682c?auto?04/08 at90can32/64/128 3.8.2 interrupt response time the interrupt execution response for all the enable d avr interrupts is four clock cycles mini- mum. after four clock cycles the program vector add ress for the actual interrupt handling routine is executed. during this four clock cycle period, t he program counter is pushed onto the stack. the vector is normally a jump to the interrupt rout ine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi-cyc le instruction, this instruction is completed before the interrupt is served. if an interrupt occ urs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine takes f our clock cycles. during these four clock cycles, the program counter (two bytes) is popped b ack from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set.
18 7682c?auto?04/08 at90can32/64/128 4. memories this section describes the different memories in th e at90can32/64/128. the avr architecture has two main memory spaces, the data memory and the program memory space. in addition, the at90can32/64/128 features an eeprom memory for data storage. all three memory spaces are linear and regular. notes: 1. byte address. 2. word (16-bit) address. 4.1 in-system reprogrammable flash program memory the at90can32/64/128 contains on-chip in-system rep rogrammable flash memory for pro- gram storage (see ?flash size?). since all avr inst ructions are 16 or 32 bits wide, the flash is organized as 16 bits wide. for software security, t he flash program memory space is divided into two sections, boot program section and applica tion program section. the flas h memory has an endur ance of at leas t 10,00 0 write/eras e cyc les. t he at90can32/64/128 program counter (pc) address the p rogram memory locations. the opera- tion of boot program section and associated boot lo ck bits for software protection are described in detail in ?boot loader support ? read-while-write self-progra mming? on page 320 . ?memory programming? on page 335 contains a detailed description on flash data seri al downloading using the spi pins or the jtag interface. table 4-1. memory mapping. memory mnemonic at90can32 at90can64 at90can128 flash size flash size 32 k bytes 64 k bytes 128 k bytes start address - 0x00000 end address flash end 0x07fff (1) 0x3fff (2) 0x0ffff (1) 0x7fff (2) 0x1ffff (1) 0xffff (2) 32 registers size - 32 bytes start address - 0x0000 end address - 0x001f i/o registers size - 64 bytes start address - 0x0020 end address - 0x005f ext i/o registers size - 160 bytes start address - 0x0060 end address - 0x00ff internal sram size isram size 2 k bytes 4 k bytes 4 k bytes start address isram start 0x0100 end address isram end 0x08ff 0x10ff 0x10ff external memory size xmem size 0-64 k bytes start address xmem start 0x0900 0x1100 0x1100 end address xmem end 0xffff eeprom size e2 size 1 k bytes 2 k bytes 4 k bytes start address - 0x0000 end address e2 end 0x03ff 0x07ff 0x0fff
19 7682c?auto?04/08 at90can32/64/128 constant tables can be allocated within the entire program memory address space (see the lpm ? load program memory and elpm ? extended load program memory instruction description). timing diagrams for instruction fetch and execution are presented in ?instruction execution tim- ing? on page 14 . figure 4-1. program memory map 4.2 sram data memory figure 4-2 shows how the at90can32/64/128 sram memory is orga nized. the at90can32/64/128 is a complex microcontroller w ith more peripheral units than can be supported within the 64 locations reserved in the o pcode for the in and out instructions. for the extended i/o space in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the lower data memory locations address both the re gister file, the i/o memory, extended i/o memory, and the internal data sram. the first 32 lo cations address the register file, the next 64 location the standard i/o memory, then 160 locat ions of extended i/o memory, and the next locations address the internal data sram (see ?isra m size?). an optional external data sram can be used with the at90can32/64/128. this sram will occupy an area in the remaining address locations i n the 64k address space. this area starts at the address following the internal sram. the regist er file, i/o, extended i/o and internal sram occupies the lowest bytes, so when using 64 kb (65, 536 bytes) of external memory, ?xmem size? bytes of external memory are available. see ?external memory interface? on page 27 for details on how to take advantage of the extern al memory map. 0x0000 flash end program memory application flash section boot flash section
20 7682c?auto?04/08 at90can32/64/128 4.2.1 sram data access when the addresses accessing the sram memory space exceeds the internal data memory locations, the external data sram is accessed using the same instructions as for the internal data memory access. when the internal data memories are accessed, the read and write strobe pins (pg0 and pg1 ) are inactive during the whole access cycle. exter nal sram operation is enabled by setting the sre bit in the xmcra register. accessing external sram takes one additional clock cycle per byte compared to access of the internal sram. this means that the commands ld, st, lds, sts, ldd, std, push, and pop take one additional clock cycle. if the stack is pl aced in external sram, interrupts, subroutine calls and returns take three clock cycles extra bec ause the two-byte program counter is pushed and popped, and external memory access does not tak e advantage of the internal pipe-line memory access. when external sram interface is used with wait-state, one-byte external access takes two, three, or four additional clock c ycles for one, two, and three wait-states respectively. interrupts, subroutine calls and retu rns will need five, seven, or nine clock cycles more than specified in the instruction set manual f or one, two, and three wait-states. the five different addressing modes for the data me mory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and in direct with post-increment. in the register file, registers r26 to r31 feature the indirect add ressing pointer registers. the direct addressing reaches the entire data space . the indirect with displacement mode reaches 63 addr ess locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decreme nted or incremented. the 32 general purpose working registers, 64 i/o re gisters, 160 extended i/o registers, and the ?isram size? bytes of internal data sram in the at90can32/64/128 are all accessible through all these addressing modes. the register fi le is described in ?general purpose regis- ter file? on page 12 .
21 7682c?auto?04/08 at90can32/64/128 figure 4-2. data memory map 4.2.2 sram data access times this section describes the general access timing co ncepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 4-3 . figure 4-3. on-chip data sram access cycles 32 registers 64 i/o registers internal sram (isram size) 0x0000 - 0x001f 0x0020 - 0x005f xmem start isram end 0xffff 0x0060 - 0x00ff data memory external sram (xmem size) 160 ext i/o reg. isram start clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction
22 7682c?auto?04/08 at90can32/64/128 4.3 eeprom data memory the at90can32/64/128 contains eeprom memory (see ?e 2 size?). it is organized as a sepa- rate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specifying the eeprom a ddress registers, the eeprom data reg- ister, and the eeprom control register. for a detailed description of spi, jtag and paralle l data downloading to the eeprom, see ?spi serial programming overview? on page 347 , ?jtag programming overview? on page 351 , and ?parallel programming overview? on page 338 respectively. 4.3.1 eeprom read/write access the eeprom access registers are accessible in the i /o space. the write access time for the eeprom is given in table 4-2 . a self-timing function, however, lets the user software detect when the next byte ca n be written. if the user code contains instruc- tions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than speci fied as minimum for the clock frequency used. see ?preventing eeprom corruption? on page 26. for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eeprom control regi ster for details on this. when the eeprom is read, the cpu is halted for four clock cycles before the next instruction is executed. when the eeprom is written, the cpu is ha lted for two clock cycles before the next instruction is executed. 4.3.2 the eeprom address registers ? eearh and eearl ? bits 15..12 ? reserved bits these bits are reserved bits in the at90can32/64/12 8 and will always read as zero. ? bits 11..0 ? eear11..0: eeprom address the eeprom address registers ? eearh and eearl spec ify the eeprom address in the eeprom space (see ?e2 size?). the eeprom data bytes are addressed linearly between 0 and ?e2 end?. the initial value of eear is undefine d. a proper value must be written before the eeprom may be accessed. ? at90can32: eear11 & eear10 exist as register bit b ut they are not used for addressing. ? at90can64: eear11 exists as register bit but it is not used for addressing. bit 15 14 13 12 11 10 9 8 ? ? ? ? eear11 eear10 eear9 eear8 eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 7 6 5 4 3 2 1 0 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 x x x x x x x x x x x x
23 7682c?auto?04/08 at90can32/64/128 4.3.3 the eeprom data register ? eedr ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register c ontains the data to be written to the eeprom in the address given by the eear register. f or the eeprom read operation, the eedr contains the data read out from the eeprom at the address given by eear. 4.3.4 the eeprom control register ? eecr ? bits 7..4 ? reserved bits these bits are reserved bits in the at90can32/64/12 8 and will always read as zero. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready inter rupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom re ady interrupt generates a constant inter- rupt when eewe is cleared. ? bit 2 ? eemwe: eeprom master write enable the eemwe bit determines whether setting eewe to on e causes the eeprom to be written. when eemwe is set, setting eewe within four clock c ycles will write data to the eeprom at the selected address if eemwe is zero, setting eewe will have no effect. when eemwe has been written to one by software, hardware clears th e bit to zero after four clock cycles. see the description of the eewe bit for an eeprom write pro cedure. ? bit 1 ? eewe: eeprom write enable the eeprom write enable signal eewe is the write st robe to the eeprom. when address and data are correctly set up, the eewe bit must be written to one to write the value into the eeprom. the eemwe bit must be written to one before a logical one is written to eewe, oth- erwise no eeprom write takes place. the following p rocedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essen tial): 1. wait until eewe becomes zero. 2. wait until spmen (store program memory enable) in spmcsr (store program mem- ory control and status register) becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eemwe bit while writin g a zero to eewe in eecr. 6. within four clock cycles after setting eemwe, wri te a logical one to eewe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is completed before initiating a new eeprom write. step 2 is only relevant if the software contains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the c pu, step 2 can be omitted. see ?boot loader bit 7 6 5 4 3 2 1 0 eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? ? ? eerie eemwe eewe eere eecr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 x 0
24 7682c?auto?04/08 at90can32/64/128 support ? read-while-write self-programming? on pag e 320 for details about boot programming. caution: an interrupt between step 5 and step 6 will make t he write cycle fail, since the eeprom master write enable will time-out. if an int errupt routine accessing the eeprom is interrupting another eeprom access, the eear or eed r register will be modified, causing the interrupted eeprom access to fail. it is recommende d to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eewe bi t is cleared by hardware. the user soft- ware can poll this bit and wait for a zero before w riting the next byte. when eewe has been set, the cpu is halted for two cycles before the next in struction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read stro be to the eeprom. when the correct address is set up in the eear register, the eere bi t must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instr uction, and the requested data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll the eewe bit before starting t he read operation. if a write operation is in progress, it is neither possible to read the eeprom , nor to change the eear register. the calibrated oscillator is used to time the eepro m accesses. table 4-2 lists the typical pro- gramming time for eeprom access from the cpu. table 4-2. eeprom programming time. symbol number of calibrated rc oscillator cycles typ programming time eeprom write (from cpu) 67 584 8.5 ms
25 7682c?auto?04/08 at90can32/64/128 the following code examples show one assembly and o ne c function for writing to the eeprom. the examples assume that interrupts are con trolled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during exec ution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any ongoin g spm command to finish. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eemwe sbi eecr,eemwe ; start eeprom write by setting eewe sbi eecr,eewe ret c code example void eeprom_write ( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 26 7682c?auto?04/08 at90can32/64/128 the next code examples show assembly and c function s for reading the eeprom. the exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. 4.3.5 preventing eeprom corruption during periods of low v cc, the eeprom data can be corrupted because the supply voltage is too low for the cpu and the eeprom to operate prope rly. these issues are the same as for board level systems using eeprom, and the same desi gn solutions should be applied. an eeprom data corruption can be caused by two situ ations when the voltage is too low. first, a regular write sequence to the eeprom requires a m inimum voltage to operate correctly. sec- ondly, the cpu itself can execute instructions inco rrectly, if the supply voltage is too low. eeprom data corruption can easily be avoided by fol lowing this design recommendation: keep the avr reset active (low) during periods of i nsufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod). if the detection level of the internal bod does not match the needed detection level, an e xternal low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is su fficient. assembly code example eeprom_read: ; wait for completion of previous write sbic eecr,eewe rjmp eeprom_read ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; start eeprom read by writing eere sbi eecr,eere ; read data from data register in r16,eedr ret c code example unsigned char eeprom_read( unsigned int uiaddress) { /* wait for completion of previous write */ while(eecr & (1< 27 7682c?auto?04/08 at90can32/64/128 4.4 i/o memory the i/o space definition of the at90can32/64/128 is shown in ?register summary? on page 384 . all at90can32/64/128 i/os and peripherals are place d in the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std instru ctions, transferring data between the 32 general purpose working registers and the i/o sp ace. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the s bi and cbi instructions. in these registers, the value of single bits can be checked by using the sb is and sbic instructions. refer to the instruction set section for more details. when usin g the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addres sing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the at90can32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd in structions can be used. for compatibility with future devices, reserved bit s should be written to zero if accessed. reserved i/o memory addresses should never be writt en. some of the status flags are cleared by writing a l ogical one to them. note that, unlike most other avr?s, the cbi and sbi instructions will only opera te on the specified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. the i/o and peripherals control registers are expla ined in later sections. 4.5 external memory interface with all the features the external memory interface provides, it is well suited to operate as an interface to memory devices such as external sram a nd flash, and peripherals such as lcd- display, a/d, and d/a. the main features are: ? four different wait-state settings (including no w ait-state). ? independent wait-state setting for different exter nal memory sectors (configurable sector size). ? the number of bits dedicated to address high byte is selectable. ? bus keepers on data lines to minimize current cons umption (optional). 4.5.1 overview when the e x ternal mem ory (xmem) is enabled, address space outside the in ternal sram becomes available using the dedicated external memo ry pins (see figure 1-2 on page 5 , table 9-3 on page 74 , table 9-9 on page 78 , and table 9-21 on page 88 ). the memory configuration is shown in figure 4-4 .
28 7682c?auto?04/08 at90can32/64/128 figure 4-4. external memory with sector select 4.5.2 using the external memory interface the interface consists of: ? ad7:0: multiplexed low-order address bus and data bus. ? a15:8: high-order address bus (configurable number of bits). ? ale: address latch enable. ? rd : read strobe. ? wr : write strobe. the control bits for the external memory interface are located in two registers, the external memory control register a ? xmcra, and the external memory control register b ? xmcrb. when the xmem interface is enabled, the xmem interf ace will override the setting in the data direction registers that corresponds to the ports d edicated to the xmem interface. for details about the port override, see the alternate function s in section ?i/o-ports? on page 66 . the xmem interface will auto-detect whether an access is int ernal or external. if the access is external, the xmem interface will output address, data, and the c ontrol signals on the ports according to fig- ure 4-6 (this figure shows the wave forms without wait-sta tes). when ale goes from high-to-low, there is a valid address on ad7:0. ale is low durin g a data transfer. when the xmem interface is enabled, also an internal access will cause acti vity on address, data and ale ports, but the rd and wr strobes will not toggle during internal access. wh en the external memory interface is disabled, the normal pin and data direction sett ings are used. note that when the xmem inter- face is disabled, the address space above the inter nal sram boundary is not mapped into the internal sram. figure 4-5 illustrates how to connect an external sram to the avr using an octal latch (typically ?74x573? or equivalent) whic h is transparent when g is high. 0x0000 isram end external memory (0-64k x 8) 0xffff internal memory srl[2..0] srw11 srw10 srw01 srw00 lower sector upper sector xmem start
29 7682c?auto?04/08 at90can32/64/128 4.5.3 address latch requirements due to the high-speed operation of the xram interfa ce, the address latch must be selected with care for system frequencies above 8 mhz @ 4v and 4 mhz @ 2.7v. when operating at condi- tions above these frequencies, the typical old styl e 74hc series latch becomes inadequate. the external memory interface is designed in compliance to the 74ahc series latch. however, most latches can be used as long they comply with the ma in timing parameters. the main parameters for the address latch are: ? d to q propagation delay (t pd ). ? data setup time before g low (t su ). ? data (address) hold time after g low ( th ). the external memory interface is designed to guaran ty minimum address hold time after g is asserted low of t h = 5 ns. refer to t laxx_ld / t llaxx_st in ?memory programming? tables 26-7 through tables 26-14. the d-to-q propagation delay (t pd ) must be taken into consideration when calculating the access time requirement of the external component. the data setup time before g low (t su ) must not exceed address valid to ale low (t avllc ) minus pcb wiring delay (dependent on the capacitive load). figure 4-5. external sram connected to the avr 4.5.4 pull-up and bus-keeper the pull-ups on the ad7:0 ports may be activated if the corresponding port register is written to one. to reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the port register to zero before entering s leep. the xmem interface also provides a bus-keeper on th e ad7:0 lines. the bus-keeper can be dis- abled and enabled in software as described in ?external memory control register b ? xmcrb? on page 33 . when enabled, the bus-keeper will ensure a define d logic level (zero or one) on the ad7:0 bus when these lines would otherwise be tri-s tated by the xmem interface. 4.5.5 timing external memory devices have different timing requi rements. to meet these requirements, the at90can32/64/128 xmem interface provides four diffe rent wait-states as shown in table 4-4 . it is important to consider the timing specification o f the external memory device before selecting the wait-state. the most important parameters are t he access time for the external memory compared to the set-up requirement of the at90can32 /64/128. the access time for the exter- nal memory is defined to be the time from receiving the chip select/address until the data of this d[7:0] a[7:0] a[15:8] rd wr sram d q g ad7:0 ale a15:8 rd wr avr
30 7682c?auto?04/08 at90can32/64/128 address actually is driven on the bus. the access t ime cannot exceed the time from the ale pulse must be asserted low until data is stable dur ing a read sequence (see t llrl + t rlrh - t dvrh in tables 26-7 through tables 26-14). the different wait-states are set up in software. as an additional feature, it is possible to divide the ex ternal memory space in two sectors with individ- ual wait-state settings. this makes it possible to connect two different memory devices with different timing requirements to the same xmem inte rface. for xmem interface timing details, please refer to tables 26-7 through tables 26-14 an d figure 26-6 to figure 26-9 in the ?external data memory characteristics? on page 374 . note that the xmem interface is asynchronous and th at the waveforms in the following figures are related to the internal system clock. the skew between the internal and external clock (xtal1) is not guarantied (varies between devices t emperature, and supply voltage). conse- quently, the xmem interface is not suited for synch ronous operation. figure 4-6. external data memory cycles no wait-state (srwn1=0 and srwn0=0) (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t4 is only present if the next instruction accesses the ram (internal or external). figure 4-7. external data memory cycles with srwn1 = 0 and srwn 0 = 1 (1) ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) xxxxx xxxxxxxx ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4
31 7682c?auto?04/08 at90can32/64/128 note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t5 is only present if the n ext instruction accesses the ram (internal or external). figure 4-8. external data memory cycles with srwn1 = 1 and srwn 0 = 0 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t6 is only present if the n ext instruction accesses the ram (internal or external). figure 4-9. external data memory cycles with srwn1 = 1 and srwn 0 = 1 (1) note: 1. srwn1 = srw11 (upper sector) or srw01 (lower sector), srwn0 = srw10 (upper sector) or srw00 (lower sector). the ale pulse in period t7 is only present if the n ext instruction accesses the ram (internal or external). ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data prev. data address data prev. data address da7:0 (xmbk = 1) system clock (clk cpu ) t4 t5 t6
32 7682c?auto?04/08 at90can32/64/128 4.5.6 external memory control register a ? xmcra ? bit 7 ? sre: external sram/xmem enable writing sre to one enables the external memory inte rface.the pin functions ad7:0, a15:8, ale, wr , and rd are activated as the alternate pin functions. the sre bit overrides any pin direction settings in the respective data direction registers. writing sre to zero, disables the external memory interface and the normal pin and da ta direction settings are used. note that when the xmem interface is disabled, the address sp ace above the internal sram boundary is not mapped into the internal sram. ? bit 6..4 ? srl2, srl1, srl0: wait-state sector lim it it is possible to configure different wait-states f or different external memory addresses. the external memory address space can be divided in two sectors that have separate wait-state bits. the srl2, srl1, and srl0 bits select the split of t he sectors, see table 4-3 and figure 4-4 . by default, the srl2, srl1, and srl0 bits are set to z ero and the entire external memory address space is treated as one sector. when the entire sra m address space is configured as one sec- tor, the wait-states are configured by the srw11 an d srw10 bits. note: 1. see table 4-1 on page 18 for ?xmem start? setting. bit 7 6 5 4 3 2 1 0 sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 xmcra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-3. sector limits with different settings of srl2..0 srl2 srl1 srl0 sector addressing 0 0 0 lower sector n/a upper sector ?xmem start? (1) - 0xffff 0 0 1 lower sector ?xmem start? (1) - 0x1fff upper sector 0x2000 - 0xffff 0 1 0 lower sector ?xmem start? (1) - 0x3fff upper sector 0x4000 - 0xffff 0 1 1 lower sector ?xmem start? (1) - 0x5fff upper sector 0x6000 - 0xffff 1 0 0 lower sector ?xmem start? (1) - 0x7fff upper sector 0x8000 - 0xffff 1 0 1 lower sector ?xmem start? (1) - 0x9fff upper sector 0xa000 - 0xffff 1 1 0 lower sector ?xmem start? (1) - 0xbfff upper sector 0xc000 - 0xffff 1 1 1 lower sector ?xmem start? (1) - 0xdfff upper sector 0xe000 - 0xffff
33 7682c?auto?04/08 at90can32/64/128 ? bit 3..2 ? srw11, srw10: wait-state select bits fo r upper sector the srw11 and srw10 bits control the number of wait -states for the upper sector of the exter- nal memory address space, see table 4-4 . ? bit 1..0 ? srw01, srw00: wait-state select bits fo r lower sector the srw01 and srw00 bits control the number of wait -states for the lower sector of the exter- nal memory address space, see table 4-4 . note: 1. n = 0 or 1 (lower/upper sector). for further details of the timing and wait-states o f the external memory interface, see figures 4-6 through figures 4-9 for how the setting of the srw bits affects the timing. 4.5.7 external memory control register b ? xmcrb ? bit 7? xmbk: external memory bus-keeper enable writing xmbk to one enables the bus keeper on the a d7:0 lines. when the bus keeper is enabled, it will ensure a defined logic level (zero or one) on ad7:0 when they would otherwise be tri-stated. writing xmbk to zero disables the bu s keeper. xmbk is not qualified with sre, so even if the xmem interface is disabled, the bus kee pers are still activated as long as xmbk is one. ? bit 6..4 ? reserved bits these are reserved bits and will always read as zer o. when writing to this address location, write these bits to zero for compatibility with fut ure devices. ? bit 2..0 ? xmm2, xmm1, xmm0: external memory high mask when the external memory is enabled, all port c pin s are default used for the high address byte. if the full address space is not required to access the external memory, some, or all, port c pins can be released for normal port pin function as des cribed in table 4-5 . as described in ?using all 64kb locations of external memory? on page 35 , it is possible to use the xmmn bits to access all 64kb locations of the external memory. table 4-4. wait states (1) srwn1 srwn0 wait states 0 0 no wait-states 0 1 wait one cycle during read/write strobe 1 0 wait two cycles during read/write strobe 1 1 wait two cycles during read/write and wait one cycl e before driving out new address bit 7 6 5 4 3 2 1 0 xmbk ? ? ? ? xmm2 xmm1 xmm0 xmcrb read/write r/w r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
34 7682c?auto?04/08 at90can32/64/128 4.5.8 using all locations of external memory smaller than 64 kb since the external memory is mapped after the inter nal memory as shown in figure 4-4 , the external memory is not addressed when addressing th e first ?isram size? bytes of data space. it may appear that the first ?isram size? bytes of the external memory are inaccessible (external memory addresses 0x0000 to ?isram end?). however, w hen connecting an external memory smaller than 64 kb, for example 32 kb, these locati ons are easily accessed simply by address- ing from address 0x8000 to ?isram end + 0x8000?. si nce the external memory address bit a15 is not connected to the external memory, addresses 0x8000 to ?isram end + 0x8000? will appear as addresses 0x0000 to ?isram end? for the e xternal memory. addressing above address ?isram end + 0x8000? is not recommended, si nce this will address an external mem- ory location that is already accessed by another (l ower) address. to the application software, the external 32 kb memory will appear as one linear 32 kb address space from ?xmem start? to ?xmem start + 0x8000?. this is illustrated in figure 4-10 . figure 4-10. address map with 32 kb external memory table 4-5. port c pins released as normal port pins when the e xternal memory is enabled xmm2 xmm1 xmm0 # bits for external memory address relea sed port pins 0 0 0 8 (full external memory space) none 0 0 1 7 pc7 0 1 0 6 pc7 .. pc6 0 1 1 5 pc7 .. pc5 1 0 0 4 pc7 .. pc4 1 0 1 3 pc7 .. pc3 1 1 0 2 pc7 .. pc2 1 1 1 no address high bits full port c (unused) internal memory 0x0000 xmem start isram end 0xffff avr memory map external memory 0x8000 0x7fff xmem start + 0x8000 isram end + 0x8000 external 32k sram (size=0x8 0x7fff 0x0000 xmem start isram end
35 7682c?auto?04/08 at90can32/64/128 4.5.9 using all 64kb locations of external memory since the external memory is mapped after the inter nal memory as shown in figure 4-4 , only (64k-(?isram size?+256)) bytes of external memory i s available by default (address space 0x0000 to ?isram end? is reserved for internal memo ry). however, it is possible to take advan- tage of the entire external memory by masking the h igher address bits to zero. this can be done by using the xmmn bits and control by software the most significant bits of the address. by set- ting port c to output 0x00, and releasing the most significant bits for normal port pin operation, the memory interface will address 0x0000 - 0x1fff. see the following code examples. note: 1. the example code assumes that the part speci fic header file is included. care must be exercised using this option as most of the memory is masked away. assembly code example (1) ; offset is defined to 0x2000 to ensure ; external memory access ; configure port c (address high byte) to ; output 0x00 when the pins are released ; for normal port pin operation ldi r16, 0xff out ddrc, r16 ldi r16, 0x00 out portc, r16 ; release pc7:5 ldi r16, (1< 36 7682c?auto?04/08 at90can32/64/128 4.6 general purpose i/o registers the at90can32/64/128 contains three general purpose i/o registers. these registers can be used for storing any information, and they are part icularly useful for storing global variables and status flags. the general purpose i/o register 0, within the addr ess range 0x00 - 0x1f, is directly bit-acces- sible using the sbi, cbi, sbis, and sbic instructio ns. 4.6.1 general purpose i/o register 0 ? gpior0 4.6.2 general purpose i/o register 1 ? gpior1 4.6.3 general purpose i/o register 2 ? gpior2 bit 7 6 5 4 3 2 1 0 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gp ior00 gpior0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 gpior17 gpior16 gpior15 gpior14 gpior13 gpior12 gpior11 gp ior10 gpior1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gp ior20 gpior2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
37 7682c?auto?04/08 at90can32/64/128 5. system clock 5.1 clock systems and their distribution figure 5-1 presents the principal clock systems in the avr an d their distribution. all of the clocks need not be active at a given time. in order to red uce power consumption, the clocks to unused modules can be halted by using different sleep mode s, as described in ?power management and sleep modes? on page 46 . the clock systems are detailed below. figure 5-1. clock distribution 5.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system conc erned with operation of the avr core. examples of such modules are the general purpose re gister file, the status register and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 5.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o mo dules, like timer/counters, spi, can, usart. the i/o clock is also used by the external i nterrupt module, but note that some external interrupts are detected by asynchronous logic, allo wing such interrupts to be detected even if the i/o clock is halted. also note that address recogni tion in the twi module is carried out asynchro- nously when clk i/o is halted, enabling twi address reception in all s leep modes. 5.1.3 flash clock ? clk flash the flash clock controls operation of the flash int erface. the flash clock is usually active simul- taneously with the cpu clock. general i/o modules can controller cpu core ram clk i/o clk asy avr clock control unit clk cpu flash and eeprom clk flash source clock watchdog timer watchdog oscillator reset logic prescaler clock multiplexer multiplexer ckout fuse clko watchdog clock calibrated rc oscillator timer/counter2 oscillator external clock crystal oscillator low-frequency crystal oscillator external clock adc clk adc asynchronous timer/counter2 timer/counter2 tosc2 xtal2 tosc1 xtal1
38 7682c?auto?04/08 at90can32/64/128 5.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronou s timer/counter to be clocked directly from an external clock or an external 32 khz clock crystal. the dedicated clock domain allows using this timer/counter as a real-time counter eve n when the device is in sleep mode. 5.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circu itry. this gives more accurate adc conversion results. 5.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ? 0? means programmed. the various choices for each clocking option is giv en in the following sections. when the cpu wakes up from power-down or power-save, the selecte d clock source is used to time the start- up, ensuring stable oscillator operation before ins truction execution starts. when the cpu starts from reset, there is an additional delay allowing t he power to reach a stable level before starting normal operation. the watchdog oscillator is used f or timing this real-time part of the start-up time. the number of wdt oscillator cycles used for each time-out is shown in table 5-2 . the frequency of the watchdog oscillator is voltage dep endent as shown in ?at90can32/64/128 typical characteristics? on page 383 . 5.3 default clock source the device is shipped with cksel = ?0010?, sut = ?1 0?, and ckdiv8 programmed. the default clock source setting is the internal rc oscillator with longest start-up time and an initial system clock prescaling of 8. this default setting ensures that all users can make their desired clock source setting using an in-system or parallel progr ammer. table 5-1. device clocking options select (1) device clocking option cksel3..0 external crystal/ceramic resonator 1111 - 1000 external low-frequency crystal 0111 - 0100 calibrated internal rc oscillator 0010 external clock 0000 reserved 0011, 0001 table 5-2. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 4.1 ms 4.3 ms 4k (4,096) 65 ms 69 ms 64k (65,536)
39 7682c?auto?04/08 at90can32/64/128 5.4 crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an on-chip oscillator, as shown in figure 5-2 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in u se, the amount of stray capacitance, and the electromagnetic noise of the environment. some init ial guidelines for choosing capacitors for use with crystals are given in table 5-3 . for ceramic resonators, the capacitor values give n by the manufacturer should be used. for more informati on on how to choose capacitors and other details on oscillator operation, refer to the multi -purpose oscillator application note. figure 5-2. crystal oscillator connections the oscillator can operate in three different modes , each optimized for a specific frequency range. the operating mode is selected by the fuses cksel3..1 as shown in table 5-3 . note: 1. this option should not be used with crystals , only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses sel ect the start-up times as shown in table 5-4 . table 5-3. crystal oscillator operating modes cksel3..1 frequency range (mhz) recommended range for capacitors c1 and c2 for use with crystals (pf) 100 (1) 0.4 - 0.9 12 - 22 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 16.0 12 - 22 xtal2 xtal1 gnd c2 c1
40 7682c?auto?04/08 at90can32/64/128 notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with ceramic r esonators and will ensure frequency stability at start-up. they can also be used with crystals wh en not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 5.5 low-frequency crystal oscillator to use a 32.768 khz watch crystal as the clock sour ce for the device, the low-frequency crystal oscillator must be selected by setting the cksel fu ses to ?0100?, ?0101?, ?0110?, or ?0111?. the crystal should be connected as shown in figure 5-3 . figure 5-3. low-frequency crystal oscillator connections 12-22 pf capacitors may be necessary if the parasit ic impedance (pads, wires & pcb) is very low. table 5-4. start-up times for the oscillator clock selection cksel0 sut1..0 start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) recommended usage 0 00 258 ck (1) 14 ck + 4.1 ms ceramic resonator, fast rising power 0 01 258 ck (1) 14 ck + 65 ms ceramic resonator, slowly rising power 0 10 1k ck (2) 14 ck ceramic resonator, bod enabled 0 11 1k ck (2) 14 ck + 4.1 ms ceramic resonator, fast rising power 1 00 1k ck (2) 14 ck + 65 ms ceramic resonator, slowly rising power 1 01 16k ck 14 ck crystal oscillator, bod enabled 1 10 16k ck 14 ck + 4.1 ms crystal oscillator, fast rising power 1 11 16k ck 14 ck + 65 ms crystal oscillator, slowly rising power xtal2 xtal1 gnd 12 - 22 pf 12 - 22 pf 32.768 khz
41 7682c?auto?04/08 at90can32/64/128 when this oscillator is selected, start-up times ar e determined by the sut1..0 fuses as shown in table 5-5 and cksel1..0 fuses as shown in table 5-6 . note: 1. these options should only be used if frequen cy stability at start-up is not important for the application 5.6 calibrated internal rc oscillator the calibrated internal rc oscillator provides a fi xed 8.0 mhz clock. the frequency is nominal value at 3v and 25 c. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse must be programmed in order to d ivide the internal frequency by 8 dur- ing start-up. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 44. for more details. this clock may be selected as th e system clock by pro- gramming the cksel fuses as shown in table 5-7 . if selected, it will operate with no external components. during reset, hardware loads the calibr ation byte into the osccal register and thereby automatically calibrates the rc oscillator. at 5v and 25 c, this calibration gives a fre- quency within 10% of the nominal frequency. using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve 2% accuracy at any given v cc and temperature. when this oscillator is used as th e chip clock, the watchdog oscil- lator will still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed calibration value, see the se ction ?calibration byte? on page 338 . note: 1. the device is shipped with this option selec ted. table 5-5. start-up times for the low-frequency crystal oscill ator clock selection sut1..0 additional delay from reset (v cc = 5.0v) recommended usage 00 14 ck fast rising power or bod enabled 01 14 ck + 4.1 ms slowly rising power 10 14 ck + 65 ms stable frequency at start-up 11 reserved table 5-6. start-up times for the low-frequency crystal oscill ator clock selection cksel3..0 start-up time from power-down and power-save recommended usage 0100 (1) 1k ck 0101 32k ck stable frequency at start-up 0110 (1) 1k ck 0111 32k ck stable frequency at start-up table 5-7. internal calibrated rc oscillator operating modes (1) cksel3..0 nominal frequency 0010 8.0 mhz
42 7682c?auto?04/08 at90can32/64/128 when this oscillator is selected, start-up times ar e determined by the sut fuses as shown in table 5-8 . note: 1. the device is shipped with this option selec ted. 5.6.1 oscillator calibration register ? osccal ? bit 7 ? reserved bit this bit is reserved for future use. ? bits 6..0 ? cal6..0: oscillator calibration value writing the calibration byte to this address will t rim the internal oscillator to remove process vari- ations from the oscillator frequency. this is done automatically during chip reset. when osccal is zero, the lowest available frequency is c hosen. writing non-zero values to this regis- ter will increase the frequency of the internal osc illator. writing 0x7f to the register gives the highest available frequency. the calibrated oscilla tor is used to time eeprom and flash access. if eeprom or flash is written, do not calib rate to more than 10% above the nominal fre- quency. otherwise, the eeprom or flash write may fa il. note that the oscillator is intended for calibration to 8.0 mhz. tuning to other values is n ot guaranteed, as indicated in table 5-9 . 5.7 external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 5-4 . to run the device on an external clock, the cksel fuses must be programmed to ?0000?. table 5-8. start-up times for the internal calibrated rc oscil lator clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14 ck bod enabled 01 6 ck 14 ck + 4.1 ms fast rising power 10 (1) 6 ck 14 ck + 65 ms slowly rising power 11 reserved bit 7 6 5 4 3 2 1 0 ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 <----- ----------- device specific cali bration value ----------- -----> table 5-9. internal rc oscillator frequency range. osccal value min frequency in percentage of nominal frequency max frequency in percentage of nominal frequency 0x00 50% 100% 0x3f 75% 150% 0x7f 100% 200%
43 7682c?auto?04/08 at90can32/64/128 figure 5-4. external clock drive configuration when this clock source is selected, start-up times are determined by the sut fuses as shown in table 5-11 . when applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a var iation in frequency of more than 2% from one clock cycle to the next can lead to unpredictab le behavior. it is required to ensure that the mcu is kept in reset during such changes in the clo ck frequency. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operati on. refer to ?system clock prescaler? on page 44 for details. 5.8 clock output buffer when the ckout fuse is programmed, the system clock will be output on clko. this mode is suitable when chip clock is used to drive other cir cuits on the system. the clock will be output also during reset and the normal operation of i/o p in will be overridden when the fuse is pro- grammed. any clock source, including internal rc os cillator, can be selected when clko serves as clock output. if the system clock prescal er is used, it is the divided system clock that is output (ckout fuse programmed). 5.9 timer/counter2 oscillator for avr microcontrollers with timer/counter2 oscill ator pins (tosc1 and tosc2), the crystal is connected directly between the pins. the oscilla tor is optimized for use with a 32.768 khz watch crystal. 12-22 pf capacitors may be necessary if the parasitic impedance (pads, wires & pcb) is very low. table 5-10. external clock frequency cksel3..0 frequency range 0000 0 - 16 mhz table 5-11. start-up times for the external clock selection sut1..0 start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) recommended usage 00 6 ck 14 ck bod enabled 01 6 ck 14 ck + 4.1 ms fast rising power 10 6 ck 14 ck + 65 ms slowly rising power 11 reserved xtal2 xtal1 gnd nc external clock signal
44 7682c?auto?04/08 at90can32/64/128 at90can32/64/128 share the timer/counter2 oscillato r pins (tosc1 and tosc2) with pg4 and pg3. this means that both pg4 and pg3 can only be used when the timer/counter2 oscil- lator is not enable. applying an external clock source to tosc1 can be d one in asynchronous operation if extclk in the assr register is written to logic one. see ?asynchronous operation of the timer/counter2? on page 159 for further description on selecting external cloc k as input instead of a 32 khz crystal. in this configuration, pg4 can not be used but pg3 is available. 5.10 system clock prescaler the at90can32/64/128 system clock can be divided by setting the clock prescaler register ? clkpr. this feature can be used to decrease power c onsumption when the requirement for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peri pherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 5-12 . 5.10.1 clock prescaler register ? clkpr ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enab le change of the clkps bits. the clkpce bit is only updated when the other bits in clkpr ar e simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bit 6..0 ? reserved bits these bits are reserved for future use. ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between the s elected clock source and the internal system clock. these bits can be written run-time to vary t he clock frequency to suit the application requirements. as the divider divides the master clo ck input to the mcu, the speed of all synchro- nous peripherals is reduced when a division factor is used. the division factors are given in table 5-12 . to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired value to cl kps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 i s programmed, clkps bits are reset to bit 7 6 5 4 3 2 1 0 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 <----- see bit description ----->
45 7682c?auto?04/08 at90can32/64/128 ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum freq uency of the device at the present operat- ing conditions. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency th an the maximum frequency of the device at the present operating conditions. the device is shi pped with the ckdiv8 fuse programmed. note: the frequency of the asynchronous clock must b e lower than 1/4th of the frequency of the scaled down source clock. otherwise, interrupts may be los t, and accessing the timer/counter2 regis- ters may fail. table 5-12. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved
46 7682c?auto?04/08 at90can32/64/128 6. power management and sleep modes sleep modes enable the application to shut down unu sed modules in the mcu, thereby saving power. the avr provides various sleep modes allowin g the user to tailor the power consump- tion to the application?s requirements. to enter any of the five sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, a nd sm0 bits in the smcr register select which sleep mode (idle, adc noise reduction, power- down, power-save, or standby) will be activated by the sleep instruction. see table 6-1 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the start-up time, executes the interru pt routine, and resumes execution from the instruction following sleep. the contents of the re gister file and sram are unaltered when the device wakes up from sleep. if a reset occurs durin g sleep mode, the mcu wakes up and exe- cutes from the reset vector. figure 5-1 on page 37 presents the different clock systems in the at90ca n32/64/128, and their distribution. the figure is helpful in selecting an appropriate sleep mode. 6.0.1 sleep mode control register ? smcr the sleep mode control register contains control bi ts for power management. ? bit 7..4 ? reserved bits these bits are reserved for future use. ? bits 3..1 ? sm2..0: sleep mode select bits 2, 1, a nd 0 these bits select between the five available sleep modes as shown in table 6-1 . note: 1. standby mode is only recommended for use wit h external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the programmer?s bit 7 6 5 4 3 2 1 0 ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 6-1. sleep mode select sm2 sm1 sm0 sleep mode 0 0 0 idle 0 0 1 adc noise reduction 0 1 0 power-down 0 1 1 power-save 1 0 0 reserved 1 0 1 reserved 1 1 0 standby (1) 1 1 1 reserved
47 7682c?auto?04/08 at90can32/64/128 purpose, it is recommended to write the sleep enabl e (se) bit to one just before the execution of the sleep instruction and to clear it immediately a fter waking up. 6.1 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing spi, can, usart , analog comparator, adc, two-wire serial interface, timer/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit com plete interrupts. if wake-up from the analog comparator interrupt is not required, the an alog comparator can be powered down by setting the acd bit in the analog comparator contro l and status register ? acsr. this will reduce power consumption in idle mode. if the adc i s enabled, a conversion starts automati- cally when this mode is entered. 6.2 adc noise reduction mode when the sm2..0 bits are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, the two-wire serial interface address watch, timer/coun ter2, can and the watchdog to continue operating (if enabled). this sleep mode basically h alts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the adc, en abling higher resolution measurements. if the adc is enabled, a conversion starts automatical ly when this mode is entered. apart from the adc conversion complete interrupt, only an external reset, a watchdog reset, a brown-out reset, a two-wire serial interface address match in terrupt, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external level inter rupt on int7:4, or an external interrupt on int3:0 can wake up the mcu from adc noise reduction mode. 6.3 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power- down mode. in this mode, the external oscillator is stopped, while the external interrupts, the two-wire serial interface address watch, and the wa tchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown-o ut reset, a two-wire serial interface address match interrupt, an external level interrup t on int7:4, or an external interrupt on int3:0 can wake up the mcu. this sleep mode basical ly halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used fo r wake-up from power-down mode, the changed level must be held for some time to wake up the mcu . refer to ?external interrupts? on page 93 for details. when waking up from power-down mode, there is a del ay from the wake-up condition occurs until the wake-up becomes effective. this allows th e clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 38 . 6.4 power-save mode when the sm2..0 bits are written to 011, the sleep instruction makes the mcu enter power- save mode. this mode is identical to power-down, wi th one exception:
48 7682c?auto?04/08 at90can32/64/128 if timer/counter2 is clocked asynchronously, i.e., the as2 bit in assr is set, timer/counter2 will run during sleep. the device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding time r/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if the asynchronous timer is not clocked asynchronously, power-down mode is recomme nded instead of power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in pow er-save mode if as2 is 0. this sleep mode basically halts all clocks except c lk asy , allowing operation only of asynchronous modules, including timer/counter2 if clocked asynch ronously. 6.5 standby mode when the sm2..0 bits are 110 and an external crysta l/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept runn ing. from standby mode, the device wakes up in 6 clock cycles. notes: 1. only recommended with external crystal or r esonator selected as clock source. 2. if as2 bit in assr is set. 3. only int3:0 or level interrupt int7:4. 6.6 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should b e used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operating. all functions not needed should be disabled. in particu lar, the following modules may need special consideration when trying to achieve the lowest pos sible power consumption. 6.6.1 analog to digital converter if enabled, the adc will be enabled in all sleep mo des. to save power, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to ?analog to digital converter - adc? on page 272 for details on adc operation. table 6-2. active clock domains and wake-up sources in the dif ferent sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer osc. enabled int7:0 twi address match timer 2 spm/ eeprom ready adc other i/o idle x x x x x (2) x x x x x x adc noise reduction x x x x (2) x (3) x x (2) x x power- down x (3) x power- save x (2) x (2) x (3) x x (2) standby (1) x x (3) x
49 7682c?auto?04/08 at90can32/64/128 6.6.2 analog comparator when entering idle mode, the analog comparator shou ld be disabled if not used. when entering adc noise reduction mode, the analog comparator sho uld be disabled. in other sleep modes, the analog comparator is automatically disabled. ho wever, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage refere nce will be enabled, independent of sleep mode. refer to ?analog comparator? on page 268 for details on how to configure the analog comparator. 6.6.3 brown-out detector if the brown-out detector is not needed by the appl ication, this module should be turned off. if the brown-out detector is enabled by the bodlevel f uses, it will be enabled in all sleep modes, and hence, always consume power. in the deep er sleep modes, this will contribute sig- nificantly to the total current consumption. refer to ?brown-out detection? on page 54 for details on how to configure the brown-out detector. 6.6.4 internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage reference will be disab led and it will not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 56 for details on the start-up time. 6.6.5 watchdog timer if the watchdog timer is not needed in the applicat ion, the module should be turned off. if the watchdog timer is enabled, it will be enabled in al l sleep modes, and hence, always consume power. in the deeper sleep modes, this will contrib ute significantly to the total current consump- tion. refer to ?watchdog timer? on page 57 for details on how to configure the watchdog timer . 6.6.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 70 for details on which pins are enabled. if the input buffer is enab led and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer sho uld be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current ev en in active mode. digital input buffers can be disabled by writing to the dig ital input disable registers (didr1 and didr0). refer to ?digital input disable register 1 ? didr1? on page 271 and ?digital input dis- able register 0 ? didr0? on page 291 for details. 6.6.7 jtag interface and on-chip debug system if the on-chip debug system is enabled by ocden fus e and the chip enter sleep mode, the main clock source is enabled, and hence, always con sumes power. in the deeper sleep modes,
50 7682c?auto?04/08 at90can32/64/128 this will contribute significantly to the total cur rent consumption. there are three alternative ways to avoid this: ? disable ocden fuse. ? disable jtagen fuse. ? write one to the jtd bit in mcucr. the tdo pin is left floating when the jtag interfac e is enabled while the jtag tap controller is not shifting data. if the hardware connected to the tdo pin does not pull up the logic level, power consumption will increase. note that the tdi pin for the next device in the scan chain con- tains a pull-up that avoids this problem. writing t he jtd bit in the mcucr register to one or leaving the jtag fuse unprogrammed disables the jta g interface.
51 7682c?auto?04/08 at90can32/64/128 7. system control and reset 7.1 reset 7.1.1 resetting the avr during reset, all i/o registers are set to their in itial values, and the program starts execution from the reset vector. the instruction placed at th e reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. i f the program never enables an interrupt source, the interrupt vectors are not used, and reg ular program code can be placed at these locations. this is also the case if the reset vecto r is in the application section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 7-1 shows the reset logic. table 7-1 defines the electrical parameters of the reset cir cuitry. the i/o ports of the avr are immediately reset to t heir initial state when a reset source goes active. this does not require any clock source to b e running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable leve l before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presente d in ?clock sources? on page 38 . 7.1.2 reset sources the at90can32/64/128 has five sources of reset: ? power-on reset. the mcu is reset when the supply v oltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. ? jtag avr reset. the mcu is reset as long as there is a logic one in the reset register, one of the scan chains of the jtag system. refer to the section ?boundary-scan ieee 1149.1 (jtag)? on page 299 for details.
52 7682c?auto?04/08 at90can32/64/128 figure 7-1. reset logic notes: 1. the power-on reset will not work unless the supply voltage has been below v por . 2. data from design simulation. if these conditions are not met, use of an external reset is recommended. 7.1.3 power-on reset a power-on reset (por) pulse is generated by an on- chip detection circuit. the detection level is defined in table 7-1 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up res et, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the dev ice is properly reset from power-on if v cc started from v por with a rise rate upper than v ccrr . reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data bus clock generator spike filter pull-up resistor jtrf jtag reset register watchdog oscillator sut[1:0] power-on reset circuit table 7-1. reset characteristics symbol parameter condition min. typ. max. units v pot power-on reset threshold voltage (rising) 1.4 2.3 v power-on reset threshold voltage (falling) (1) 1.3 2.3 v v por v cc start voltage to ensure internal power-on reset signal -0.05 gnd (2) 0.05 (2) v v ccrr v cc rise rate to ensure internal power-on reset signal 0.3 (2) v/ms v rst reset pin threshold voltage 0.2 v cc 0.85 v cc v t rst minimum pulse width on reset pin vcc = 5 v, temperature = 25 c 400 ns
53 7682c?auto?04/08 at90can32/64/128 v cc rise. the reset signal is activated again, without any delay, when v cc decreases below the detection level. figure 7-2. mcu start-up, reset tied to v cc figure 7-3. mcu start-up, reset extended externally note: if v por or v ccrr parameter range can not be followed, an external r eset is required. 7.1.4 external reset an external reset is generated by a low level on th e reset pin. reset pulses longer than the minimum pulse width (see table 7-1 ) will generate a reset, even if the clock is not r unning. shorter pulses are not guaranteed to generate a res et. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts t he mcu after the time-out period ? t tout ? has expired. v reset time-out internal reset t tout v pot v por cc v ccrr v ccrr v reset time-out internal reset t tout v rst v por cc v ddrr
54 7682c?auto?04/08 at90can32/64/128 figure 7-4. external reset during operation 7.1.5 brown-out detection at90can32/64/128 has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed t rigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger leve l has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detectio n level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guara nteed. the test is performed using bodlevel = 010 for low operating voltage and bodlev el = 101 for high operating volt- age . 2. not tested. cc table 7-2. bodlevel fuse coding (1) bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 3.8 4.1 4.4 v 101 4.0 (2) v 100 3.9 (2) v 011 3.8 (2) v 010 2.5 2.7 2.9 v 001 2.6 (2) v 000 2.5 (2) v table 7-3. brown-out characteristics symbol parameter min. typ. max. units v hyst brown-out detector hysteresis 70 mv t bod min pulse width on brown-out reset 2 s
55 7682c?auto?04/08 at90can32/64/128 when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 7-5 ), the brown-out reset is immediately activated. wh en v cc increases above the trigger level (v bot+ in figure 7-5 ), the delay counter starts the mcu after the time- out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in table 7-1 . figure 7-5. brown-out reset during operation 7.1.6 watchdog reset when the watchdog times out, it will generate a sho rt reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer sta rts counting the time-out period t tout . refer to page 57 for details on operation of the watchdog timer. figure 7-6. watchdog reset during operation 7.1.7 mcu status register ? mcusr the mcu status register provides information on whi ch reset source caused an mcu reset. v cc reset time-out internal reset v bot- v bot+ t tout ck cc bit 7 6 5 4 3 2 1 0 ? ? ? jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description
56 7682c?auto?04/08 at90can32/64/128 ? bit 7..5 ? reserved bits these bits are reserved for future use. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a log ic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is reset b y a power-on reset, or by writing a logic zero to the flag. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bit is reset only by writing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if t he register is cleared before another reset occurs, the source of the reset can be found by exa mining the reset flags. 7.2 internal voltage reference at90can32/64/128 features an internal bandgap refer ence. this reference is used for brown- out detection, and it can be used as an input to th e analog comparator or the adc. 7.2.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in table 7-4 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by programming the bodle vel [2..0] fuse). 2. when the bandgap reference is connected to the an alog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting th e acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-d own mode, the user can avoid the three conditions above to ensure that the reference is tu rned off before entering power-down mode.
57 7682c?auto?04/08 at90can32/64/128 7.2.2 voltage reference characteristics 7.3 watchdog timer the watchdog timer is clocked from a separate on-ch ip oscillator which runs at 1 mhz. this is the typical value at v cc = 5v. see characterization data for typical values at other v cc levels. by controlling the watchdog timer prescaler, the watch dog reset interval can be adjusted as shown in table 7-6 on page 58 . the wdr ? watchdog reset ? instruction resets the watchdog timer. the watchdog timer is also reset when it is disabled and when a chip reset occurs. eight different clock cycle periods can be selected to determine the reset period. if the reset period expires without another watchdog reset, the at90can32/64/128 resets and executes from the reset vector. for timing details on the wa tchdog reset, refer to table 7-6 on page 58 . to prevent unintentional disabling of the watchdog or unintentional change of time-out period, two different safety levels are selected by the fus e wdton as shown in table 7-5. refer to ?timed sequences for changing the configuration of the watchdog timer? on page 59 for details. figure 7-7. watchdog timer 7.3.1 watchdog timer control register ? wdtcr table 7-4. internal voltage reference characteristics symbol parameter condition min. typ. max. units v bg bandgap reference voltage 1.0 1.1 1.2 v t bg bandgap reference start-up time 40 70 s i bg bandgap reference current consumption 15 a table 7-5. wdt configuration as a function of the fuse setting s of wdton wdton safety level wdt initial state how to disable the wdt how to change time-out unprogrammed 1 disabled timed sequence timed sequence programmed 2 enabled always enabled timed sequence watchdog oscillator ~1 mhz bit 7 6 5 4 3 2 1 0
58 7682c?auto?04/08 at90can32/64/128 ? bits 7..5 ? reserved bits these bits are reserved bits for future use. ? bit 4 ? wdce: watchdog change enable this bit must be set when the wde bit is written to logic zero. otherwise, the watchdog will not be disabled. once written to one, hardware will cle ar this bit after four clock cycles. refer to the description of the wde bit for a watchdog disable p rocedure. this bit must also be set when changing the prescaler bits. see ?timed sequences for changing the configuration of the watchdog timer? on page 59. ? bit 3 ? wde: watchdog enable when the wde is written to logic one, the watchdog timer is enabled, and if the wde is written to logic zero, the watchdog timer function is disab led. wde can only be cleared if the wdce bit has logic level one. to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be writ- ten to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logic 0 to wde. this disables the watchdog. in safety level 2, it is not possible to disable th e watchdog timer, even with the algorithm described above. see ?timed sequences for changing the configuration of the watchdog timer? on page 59. ? bits 2..0 ? wdp2, wdp1, wdp0: watchdog timer presc aler 2, 1, and 0 the wdp2, wdp1, and wdp0 bits determine the watchdo g timer prescaling when the watch- dog timer is enabled. the different prescaling valu es and their corresponding timeout periods are shown in table 7-6 . ? ? ? wdce wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 7-6. watchdog timer prescale select wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 3.0v typical time-out at v cc = 5.0v 0 0 0 16k cycles 17.1 ms 16.3 ms 0 0 1 32k cycles 34.3 ms 32.5 ms 0 1 0 64k cycles 68.5 ms 65 ms 0 1 1 32/64k cycles 0.14 s 0.13 s 1 0 0 256k cycles 0.27 s 0.26 s 1 0 1 512k cycles 0.55 s 0.52 s 1 1 0 1,024k cycles 1.1 s 1.0 s 1 1 1 2,048k cycles 2.2 s 2.1 s
59 7682c?auto?04/08 at90can32/64/128 the following code example shows one assembly and o ne c function for turning off the wdt. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. note: 1. the example code assumes that the part speci fic header file is included. 7.4 timed sequences for changing the configuration o f the watchdog timer the sequence for changing configuration differs sli ghtly between the two safety levels. separate procedures are described for each level. 7.4.1 safety level 1 in this mode, the watchdog timer is initially disab led, but can be enabled by writing the wde bit to 1 without any restriction. a timed sequence is n eeded when changing the watchdog time-out period or disabling an enabled watchdog timer. to d isable an enabled watchdog timer, and/or changing the watchdog time-out, the following proce dure must be followed: 1. in the same operation, write a logic one to wdce and wde. a logic one must be writ- ten to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, in the same op eration, write the wde and wdp bits as desired, but with the wdce bit cleared. 7.4.2 safety level 2 in this mode, the watchdog timer is always enabled, and the wde bit will always read as one. a timed sequence is needed when changing the watchdog time-out period. to change the watchdog time-out, the following procedure must be followed: 1. in the same operation, write a logical one to wdc e and wde. even though the wde always is set, the wde must be written to one to st art the timed sequence. 2. within the next four clock cycles, in the same op eration, write the wdp bits as desired, but with the wdce bit cleared. the value written to the wde bit is irrelevant. assembly code example (1) wdt_off: ; write logical one to wdce and wde ldi r16, (1< 60 7682c?auto?04/08 at90can32/64/128 8. interrupts t h i s s e c t i o n d e s c r i b e s t h e s p e c i f i c s o f t h e i n t e r r u p t h a n d l i n g a s p e r f o r m e d i n at90can32/64/128. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 15 . 8.1 interrupt vectors in at90can32/64/128 table 8-1. reset and interrupt vectors vector no. program address (1) source interrupt definition 1 0x0000 (2) reset external pin, power-on reset, brown-out reset, watchdog reset, and jtag avr reset 2 0x0002 int0 external interrupt request 0 3 0x0004 int1 external interrupt request 1 4 0x0006 int2 external interrupt request 2 5 0x0008 int3 external interrupt request 3 6 0x000a int4 external interrupt request 4 7 0x000c int5 external interrupt request 5 8 0x000e int6 external interrupt request 6 9 0x0010 int7 external interrupt request 7 10 0x0012 timer2 comp timer/counter2 compare match 11 0x0014 timer2 ovf timer/counter2 overflow 12 0x0016 timer1 capt timer/counter1 capture event 13 0x0018 timer1 compa timer/counter1 compare match a 14 0x001a timer1 compb timer/counter1 compare match b 15 0x001c timer1 compc timer/counter1 compare match c 16 0x001e timer1 ovf timer/counter1 overflow 17 0x0020 timer0 comp timer/counter0 compare match 18 0x0022 timer0 ovf timer/counter0 overflow 19 0x0024 canit can transfer complete or error 20 0x0026 ovrit can timer overrun 21 0x0028 spi, stc spi serial transfer complete 22 0x002a usart0, rx usart0, rx complete 23 0x002c usart0, udre usart0 data register empty 24 0x002e usart0, tx usart0, tx complete 25 0x0030 analog comp analog comparator 26 0x0032 adc adc conversion complete 27 0x0034 ee ready eeprom ready 28 0x0036 timer3 capt timer/counter3 capture event
61 7682c?auto?04/08 at90can32/64/128 notes: 1. when the ivsel bit in mcucr is set, interru pt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash sectio n. 2. when the bootrst fuse is programmed, the device w ill jump to the boot loader address at reset, see ?boot loader support ? read-while-write self-progra mming? on page 320 . table 8-2 shows reset and interrupt vectors placement for th e various combinations of bootrst and ivsel settings. if the program never en ables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 24-6 on page 333 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in at90can32/64/128 is: ;address labels code co?ents 0x0000 jp reset ; reset handler 0x0002 jp ext_int0 ; irq0 handler 0x0004 jp ext_int1 ; irq1 handler 0x0006 jp ext_int2 ; irq2 handler 0x0008 jp ext_int3 ; irq3 handler 0x000a jp ext_int4 ; irq4 handler 0x000c jp ext_int5 ; irq5 handler 0x000e jp ext_int6 ; irq6 handler 0x0010 jp ext_int7 ; irq7 handler 29 0x0038 timer3 compa timer/counter3 compare match a 30 0x003a timer3 compb timer/counter3 compare match b 31 0x003c timer3 compc timer/counter3 compare match c 32 0x003e timer3 ovf timer/counter3 overflow 33 0x0040 usart1, rx usart1, rx complete 34 0x0042 usart1, udre usart1 data register empty 35 0x0044 usart1, tx usart1, tx complete 36 0x0046 twi two-wire serial interface 37 0x0048 spm ready store program memory ready table 8-2. reset and interrupt vectors placement (1) bootrst ivsel reset address interrupt vectors start ad dress 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 table 8-1. reset and interrupt vectors (continued) vector no. program address (1) source interrupt definition
62 7682c?auto?04/08 at90can32/64/128 0x0012 jmp tim2_comp ; timer2 compare handler 0x0014 jmp tim2_ovf ; timer2 overflow handler 0x0016 jmp tim1_capt ; timer1 capture handler 0x0018 jmp tim1_compa; timer1 comparea handler 0x001a jmp tim1_compb; timer1 compareb handler 0x001c jmp tim1_ovf ; timer1 comparec handler 0x001e jmp tim1_ovf ; timer1 overflow handler 0x0020 jmp tim0_comp ; timer0 compare handler 0x0022 jmp tim0_ovf ; timer0 overflow handler 0x0024 jmp can_it ; can handler 0x0026 jmp ctim_ovf ; can timer overflow handler 0x0028 jmp spi_stc ; spi transfer complete handler 0x002a jmp usart0_rxc; usart0 rx complete handler 0x002c jmp usart0_dre; usart0,udr empty handler 0x002e jmp usart0_txc; usart0 tx complete handler 0x0030 jmp ana_comp ; analog comparator handler 0x0032 jmp adc ; adc conversion complete handler 0x0034 jmp ee_rdy ; eeprom ready handler 0x0036 jmp tim3_capt ; timer3 capture handler 0x0038 jmp tim3_compa; timer3 comparea handler 0x003a jmp tim3_compb; timer3 compareb handler 0x003c jmp tim3_compc; timer3 comparec handler 0x003e jmp tim3_ovf ; timer3 overflow handler 0x0040 jmp usart1_rxc; usart1 rx complete handler 0x0042 jmp usart1_dre; usart1,udr empty handler 0x0044 jmp usart1_txc; usart1 tx complete handler 0x0046 jmp twi ; twi interrupt handler 0x0048 jmp spm_rdy ; spm ready handler ; 0x004a reset: ldi r16, high(ramend) ; main program star t 0x004b out sph,r16 ;set stack pointer to top of ram 0x004c ldi r16, low(ramend) 0x004d out spl,r16 0x004e sei ; enable interrupts 0x004f xxx ... ... ... ... when the bootrst fuse is unprogrammed, the boot sec tion size set to 8k bytes and the ivsel bit in the mcucr register is set before any i nterrupts are enabled, the most typical and general program setup for the reset and interrupt v ector addresses is: ;address labels code comments 0x0000 reset: ldi r16,high(ramend) ; main program start 0x0001 out sph,r16 ; set stack pointer to top of ram 0x0002 ldi r16,low(ramend) 0x0003 out spl,r16
63 7682c?auto?04/08 at90can32/64/128 0x0004 sei ; enable interrupts 0x0005 xxx ; .org (bootresetadd + 0x0002) 0x..02 jmp ext_int0 ; irq0 handler 0x..04 jmp pcint0 ; pcint0 handler ... ... ... ; 0x..0c jmp spm_rdy ; store program memory ready handle r when the bootrst fuse is programmed and the boot se ction size set to 8k bytes, the most typical and general program setup for the reset and interrupt vector addresses is: ;address labels code comments .org 0x0002 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp pcint0 ; pcint0 handler ... ... ... ; 0x002c jmp spm_rdy ; store program memory ready handle r ; .org (bootresetadd) 0x..00 reset: ldi r16,high(ramend) ; main program start 0x..01 out sph,r16 ; set stack pointer to top of ram 0x..02 ldi r16,low(ramend) 0x..03 out spl,r16 0x..04 sei ; enable interrupts 0x..05 xxx when the bootrst fuse is programmed, the boot secti on size set to 8k bytes and the ivsel bit in the mcucr register is set before any interru pts are enabled, the most typical and general program setup for the reset and interrupt vector ad dresses is: ;address labels code comments ; .org (bootresetadd) 0x..00 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x..04 jmp pcint0 ; pcint0 handler ... ... ... ; 0x..44 jmp spm_rdy ; store program memory ready handle r ; 0x..46 reset: ldi r16,high(ramend) ; main program start 0x..47 out sph,r16 ; set stack pointer to top of ram 0x..48 ldi r16,low(ramend) 0x..49 out spl,r16 0x..4a sei ; enable interrupts 0x..4b xxx
64 7682c?auto?04/08 at90can32/64/128 8.2 moving interrupts between application and boot s pace the general interrupt control register controls the placement of the interrupt vector table. 8.2.1 mcu control register ? mcucr ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (zero), the interrupt vectors are placed at the start of the flash memory. when this bit is set (one), the interrupt v ectors are moved to the beginning of the boot loader section of the flash. the actual address of the start of the boot flash section is deter- mined by the bootsz fuses. refer to the section ?boot loader support ? read-while-write self-programming? on page 320 for details. to avoid unintentional changes of int errupt vector tables, a special write procedure must be followed to change the ivsel bit: 1. write the interrupt vector change enable (ivce) b it to one. 2. within four cycles, write the desired value to iv sel while writing a zero to ivce. interrupts will automatically be disabled while thi s sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabled until after the instruction following the write to ivsel. if ivsel is not written, interrupts remain d isabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot lo ader section and boot lock bit blb02 is pro- grammed, interrupts are disabled while executing fr om the application section. if interrupt vectors are placed in the application section and boot lock bit blb12 is programed, interrupts are dis- abled while executing from the boot loader section. refer to the section ?boot loader support ? read-while-write self-programming? on page 320 for details on boot lock bits. bit 7 6 5 4 3 2 1 0 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0
65 7682c?auto?04/08 at90can32/64/128 ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cycles after it is written or when iv sel is written. setting the ivce bit will disable interrupts, as explained in the ivsel description a bove. see code example below. assembly code example move_interrupts: ; get mcucr in r16, mcucr mov r17, r16 ; enable change of interrupt vectors ori r16, (1< 66 7682c?auto?04/08 at90can32/64/128 9. i/o-ports 9.1 introduction all avr ports have true read-modify-write functiona lity when used as general digital i/o ports. this means that the direction of one port pin can b e changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when chang- ing drive value (if configured as output) or enabli ng/disabling of pull-up resistors (if configured as input). each output buffer has symmetrical drive ch aracteristics with both high sink and source capability. all port pins have individually selecta ble pull-up resistors with a supply-voltage invari- ant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 9-1 . refer to ?electrical characteristics (1)? on page 364 for a complete list of parameters. figure 9-1. i/o pin equivalent schematic all registers and bit references in this section ar e written in general form. a lower case ?x? repre- sents the numbering letter for the port, and a lowe r case ?n? represents the bit number. however, when using the register or bit defines in a program , the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented gen erally as portxn. the physical i/o regis- ters and bit locations are listed in ?register desc ription for i/o-ports?. three i/o memory address locations are allocated fo r each port, one each for the data register ? portx, data direction register ? ddrx, and the po rt input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. however, writing a logic one to a bit in the pinx r egister, will result in a toggle in the correspond- ing bit in the data register. in addition, the pull -up disable ? pud bit in mcucr disables the pull-up function for all pins in all ports when set . using the i/o port as general digital i/o is descri bed in ?ports as general digital i/o?. most port pins are multiplexed with alternate functions for t he peripheral features on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 71 . refer to the individual module sections for a ful l description of the alternate functions. note that enabling the alternate function of some o f the port pins does not affect the use of the other pins in the port as general digital i/o. c pin logic r pu see figure "general digital i/o" for details pxn
67 7682c?auto?04/08 at90can32/64/128 9.2 ports as general digital i/o the ports are bi-directional i/o ports with optiona l internal pull-ups. figure 9-2 shows a func- tional description of one i/o-port pin, here generi cally called pxn. figure 9-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 9.2.1 configuring the pin each port pin consists of three register bits: ddxn , portxn, and pinxn. as shown in ?register description for i/o-ports? on page 89 , the ddxn bits are accessed at the ddrx i/o addres s, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direc tion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is writ ten logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is conf igured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, port xn has to be written logic zero or the pin has to be configured as an output pin the port pins are tri-stated when reset condition b ecomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register
68 7682c?auto?04/08 at90can32/64/128 if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when th e pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 toggling the pin writing a logic one to pinxn toggles the value of p ortxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 9.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) occurs. normally, the p ull-up enabled state is fully acceptable, as a high-impedant environment will not notice the dif ference between a strong high driver and a pull-up. if this is not the case, the pud bit in th e mcucr register can be set to disable all pull- ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b0 0) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 9-1 summarizes the control signals for the pin value. 9.2.4 reading the pin value independent of the setting of data direction bit dd xn, the port pin can be read through the pinxn register bit. as shown in figure 9-2 , the pinxn register bit and the preceding latch co n- stitute a synchronizer. this is needed to avoid met astability if the physical pin changes value near the edge of the internal clock, but it also in troduces a delay. figure 9-3 shows a timing dia- gram of the synchronization when reading an externa lly applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 9-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no default configuration after reset. tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled l ow. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source)
69 7682c?auto?04/08 at90can32/64/128 figure 9-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after th e first falling edge of the system clock. the latch is closed when the clock is low, and goes transpare nt when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signa l value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows t pd,max and t pd,min , a single signal transition on the pin will be del ayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 9-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay t pd through the synchronizer is 1 system clock period. figure 9-4. synchronization when reading a software assigned pi n value xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd
70 7682c?auto?04/08 at90can32/64/128 the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups as signed to port pins 6 and 7. the resulting pin values are read back again, but as previously discu ssed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: 1. for the assembly program, two temporary regi sters are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the direc tion bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high d rivers. 9.2.5 digital input enable and sleep modes as shown in figure 9-2 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denoted sleep in the fi gure, is set by the mcu sleep controller in power-down mode, power-save mode, and standby mode to avoid high power consumption if some input signals are left floating, or have an an alog signal level close to v cc /2. sleep is overridden for port pins enabled as extern al interrupt pins. if the external interrupt request is not enabled, sleep is active also for th ese pins. sleep is also overridden by various other alternate functions as described in ?alternate port functions? on page 71 . if a logic high level (?one?) is present on an asyn chronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any log ic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16, (1< 71 7682c?auto?04/08 at90can32/64/128 above mentioned sleep modes, as the clamping in the se sleep modes produces the requested logic change. 9.2.6 unconnected pins if some pins are unused, it is recommended to ensur e that these pins have a defined level. even though most of the digital inputs are disabled in t he deep sleep modes as described above, float- ing inputs should be avoided to reduce current cons umption in all other modes where the digital inputs are enabled (reset, active mode and idle mod e). the simplest method to ensure a defined level of an unused pin, is to enable the in ternal pull-up. in this case, the pull-up will be disabled during reset. if low power consumption dur ing reset is important, it is recommended to use an external pull-up or pull-down. connecting un used pins directly to v cc or gnd is not rec- ommended, since this may cause excessive currents i f the pin is accidentally configured as an output. 9.3 alternate port functions most port pins have alternate functions in addition to being general digital i/os. figure 9-5 shows how the port pin control signals from the simplifie d figure 9-2 can be overridden by alternate functions. the overriding signals may not be presen t in all port pins, but the figure serves as a generic description applicable to all port pins in the avr microcontroller family.
72 7682c?auto?04/08 at90can32/64/128 figure 9-5. alternate port functions (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other s ignals are unique for each pin. table 9-2 summarizes the function of the overriding signals. the pin and port indexes from figure 9-5 are not shown in the succeeding tables. the overri ding signals are generated internally in the modules having the alternate func tion. clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q set clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx reset reset q q d clr q q d clr q q d clr pinxn portxn ddxn data bus 0 1 dieovxn sleep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value sleep: sleep control pxn i/o 0 1 ptoexn wpx ptoexn: pxn, port toggle override enable wpx: write pinx
73 7682c?auto?04/08 at90can32/64/128 the following subsections shortly describe the alte rnate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. 9.3.1 mcu control register ? mcucr table 9-2. generic description of overriding signals for alter nate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is contro lled by the puov signal. if this signal is cleared, the pull-up is e nabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled whe n puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabl ed when ddov is set/cleared, regardless of the setting of t he ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enab led, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is con trolled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, rega rdless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted . dieoe digital input enable override enable if this bit is set, the digital input enable is con trolled by the dieov signal. if this signal is cleared, the digita l input enable is determined by mcu state (normal mode, sleep mode ). dieov digital input enable override value if dieoe is set, the digital input is enabled/disab led when dieov is set/cleared, regardless of the mcu state ( normal mode, sleep mode). di digital input this is the digital input to alternate functions. i n the figure, the signal is connected to the output of the schmitt tr igger but before the synchronizer. unless the digital input i s used as a clock source, the module with the alternate functio n will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate f unctions. the signal is connected directly to the pad, and can be used bi- directionally. bit 7 6 5 4 3 2 1 0 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0
74 7682c?auto?04/08 at90can32/64/128 ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in th e i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull- ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? for more details about this featu re. 9.3.2 alternate functions of port a the port a has an alternate function as the address low byte and data lines for the external memory interface. the port a pins with alternate functions are shown in table 9-3 . the alternate pin configuration is as follows: ? ad7 ? port a, bit 7 ad7, external memory interface address 7 and data 7 . ? ad6 ? port a, bit 6 ad6, external memory interface address 6 and data 6 . ? ad5 ? port a, bit 5 ad5, external memory interface address 5 and data 5 . ? ad4 ? port a, bit 4 ad4, external memory interface address 4 and data 4 . ? ad3 ? port a, bit 3 ad3, external memory interface address 3 and data 3 . ? ad2 ? port a, bit 2 ad2, external memory interface address 2 and data 2 . ? ad1 ? port a, bit 1 ad1, external memory interface address 1 and data 1 . ? ad0 ? port a, bit 0 ad0, external memory interface address 0 and data 0 . table 9-3. port a pins alternate functions port pin alternate function pa7 ad7 (external memory interface address and data bit 7) pa6 ad6 (external memory interface address and data bit 6) pa5 ad5 (external memory interface address and data bit 5) pa4 ad4 (external memory interface address and data bit 4) pa3 ad3 (external memory interface address and data bit 3) pa2 ad2 (external memory interface address and data bit 2) pa1 ad1 (external memory interface address and data bit 1) pa0 ad0 (external memory interface address and data bit 0)
75 7682c?auto?04/08 at90can32/64/128 table 9-4 and table 9-5 relates the alternate functions of port a to the o verriding signals shown in figure 9-5 on page 72 . note: 1. ada is short for address active and represen ts the time when address is output. see ?exter- nal memory interface? on page 27 for details. note: 1. ada is short for address active and represen ts the time when address is output. see ?exter- nal memory interface? on page 27 for details. table 9-4. overriding signals for alternate functions in pa7.. pa4 signal name pa7/ad7 pa6/ad6 pa5/ad5 pa4/ad4 puoe sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) puov 0 0 0 0 ddoe sre sre sre sre ddov wr + ada wr + ada wr + ada wr + ada pvoe sre sre sre sre pvov a7 ? ada (1) + d7 output ? wr a6 ? ada (1) + d6 output ? wr a5 ? ada (1) + d5 output ? wr a4 ? ada (1) + d4 output ? wr ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di d7 input d6 input d5 input d4 input aio ? ? ? ? table 9-5. overriding signals for alternate functions in pa3.. pa0 signal name pa3/ad3 pa2/ad2 pa1/ad1 pa0/ad0 puoe sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) sre ? (ada (1) + wr ) puov 0 0 0 0 ddoe sre sre sre sre ddov wr + ada wr + ada wr + ada wr + ada pvoe sre sre sre sre pvov a3 ? ada (1) + d3 output ? wr a2 ? ada (1) + d2 output ? wr a1 ? ada (1) + d1 output ? wr a0 ? ada (1) + d0 output ? wr ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di d3 input d2 input d1 input d0 input aio ? ? ? ?
76 7682c?auto?04/08 at90can32/64/128 9.3.3 alternate functions of port b the port b pins with alternate functions are shown in table 9-6 . the alternate pin configuration is as follows: ? oc0a/oc1c, bit 7 oc0a, output compare match a output. the pb7 pin ca n serve as an external output for the timer/counter0 output compare a. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc0a pin is also the ou tput pin for the pwm mode timer function. oc1c, output compare match c output. the pb7 pin ca n serve as an external output for the timer/counter1 output compare c. the pin has to be configured as an output (ddb7 set ?one?) to serve this function. the oc1c pin is also the ou tput pin for the pwm mode timer function. ? oc1b, bit 6 oc1b, output compare match b output. the pb6 pin ca n serve as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddb6 set ?one?) to serve this function. the oc1b pin is also the ou tput pin for the pwm mode timer function. ? oc1a, bit 5 oc1a, output compare match a output. the pb5 pin ca n serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set ?one?) to serve this function. the oc1a pin is also the ou tput pin for the pwm mode timer function. ? oc2a, bit 4 oc2a, output compare match a output. the pb4 pin ca n serve as an external output for the timer/counter2 output compare a. the pin has to be configured as an output (ddb4 set ?one?) to serve this function. the oc2a pin is also the ou tput pin for the pwm mode timer function. ? miso ? port b, bit 3 miso, master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardle ss of the setting of ddb3. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb3. when the pin is forced to be an input, the pull-up can still be controlled by the portb3 bit. ? mosi ? port b, bit 2 table 9-6. port b pins alternate functions port pin alternate functions pb7 oc0a/oc1c (output compare and pwm output a for time r/counter0 or output compare and pwm output c for timer/counter1) pb6 oc1b (output compare and pwm output b for timer/ counter1) pb5 oc1a (output compare and pwm output a for timer/ counter1) pb4 oc2a (output compare and pwm output a for timer/ counter2 ) pb3 miso (spi bus master input/slave output) pb2 mosi (spi bus master output/slave input) pb1 sck (spi bus serial clock) pb0 ss (spi slave select input)
77 7682c?auto?04/08 at90can32/64/128 mosi, spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardles s of the setting of ddb2. when the spi is enabled as a master, the data direction of this pin is controlled by ddb2. when the pin is forced to be an input, the pull-up can still be controlled by the portb2 bit. ? sck ? port b, bit 1 sck, master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardles s of the setting of ddb1. when the spi is enabled as a master, the data direction of this pin is controlled by ddb1. when the pin is forced to be an input, the pull-up can still be controlled by the portb1 bit. ? ss ? port b, bit 0 ss , slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb0. as a slave , the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up can still be controlled by the portb0 bit. table 9-7 and table 9-8 relate the alternate functions of port b to the ov erriding signals shown in figure 9-5 on page 72 . spi mstr input and spi slave output constitute th e miso sig- nal, while mosi is divided into spi mstr output and spi slave input. table 9-7 and table 9-8 relates the alternate functions of port b to the o verriding signals shown in figure 9-5 on page 72 . note: 1. see ?output compare modulator - ocm? on page 164 for details. table 9-7. overriding signals for alternate functions in pb7.. pb4 signal name pb7/oc0a/oc1c pb6/oc1b pb5/oc1a pb4/oc2a puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc0a/oc1c enable (1) oc1b enable oc1a enable oc2a enable pvov oc0a/oc1c (1) oc1b oc1a oc2a ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio ? ? ? ?
78 7682c?auto?04/08 at90can32/64/128 9.3.4 alternate functions of port c the port c has an alternate function as the address high byte for the external memory interface. the port c pins with alternate functions are shown in table 9-9 . the alternate pin configuration is as follows: ? a15/clko ? port c, bit 7 a15, external memory interface address 15. clko, divided system clock: the divided system cloc k can be output on the pc7 pin. the divided system clock will be output if the ckout fu se is programmed, regardless of the portc7 and ddc7 settings. it will also be output du ring reset. table 9-8. overriding signals for alternate functions in pb3.. pb0 signal name pb3/miso pb2/mosi pb1/sck pb0/ss puoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr puov portb3 ? pud portb2 ? pud portb1 ? pud portb0 ? pud ddoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr ddov 0 0 0 0 pvoe spe ? mstr spe ? mstr spe ? mstr 0 pvov spi slave output spi master output sck output 0 ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di spi master input spi slave input ? reset sck input spi ss aio ? ? ? ? table 9-9. port c pins alternate functions port pin alternate function pc7 a15/clko (external memory interface address 15 or d ivided system clock) pc6 a14 (external memory interface address 14) pc5 a13 (external memory interface address 13) pc4 a12 (external memory interface address 12) pc3 a11 (external memory interface address 11) pc2 a10 (external memory interface address 10) pc1 a9 (external memory interface address 9) pc0 a8 (external memory interface address 8)
79 7682c?auto?04/08 at90can32/64/128 ? a14 ? port c, bit 6 a14, external memory interface address 14. ? a13 ? port c, bit 5 a13, external memory interface address 13. ? a12 ? port c, bit 4 a12, external memory interface address 12. ? a11 ? port c, bit 3 a11, external memory interface address 11. ? a10 ? port c, bit 2 a10, external memory interface address 10. ? a9 ? port c, bit 1 a9, external memory interface address 9. ? a8 ? port c, bit 0 a8, external memory interface address 8. table 9-10 and table 9-11 relate the alternate functions of port c to the ov erriding signals shown in figure 9-5 on page 72 . note: 1. ckout is one if the ckout fuse is programmed table 9-10. overriding signals for alternate functions in pc7.. pc4 signal name pc7/a15 pc6/a14 pc5/a13 pc4/a12 puoe sre ? (xmm < 1) sre ? (xmm < 2) sre ? (xmm < 3) sre ? (xmm < 4) puov 0 0 0 0 ddoe ckout (1) + (sre ? (xmm < 1)) sre ? (xmm < 2) sre ? (xmm < 3) sre ? (xmm < 4) ddov 1 1 1 1 pvoe ckout (1) + (sre ? (xmm < 1)) sre ? (xmm < 2) sre ? (xmm < 3) sre ? (xmm < 4) pvov (a15 ? ckout (1) ) + (clko ? ckout (1) ) a14 a13 a12 ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio ? ? ? ?
80 7682c?auto?04/08 at90can32/64/128 9.3.5 alternate functions of port d the port d pins with alternate functions are shown in table 9-12 . the alternate pin configuration is as follows: ? t0/clko ? port d, bit 7 t0, timer/counter0 counter source. ? rxcan/t1 ? port d, bit 6 rxcan, can receive data (data input pin for the can ). when the can controller is enabled this pin is configured as an input regardless of th e value of ddd6. when the can forces this pin to be an input, the pull-up can still be controlled by the portd6 bit. t1, timer/counter1 counter source. ? txcan/xck1 ? port d, bit 5 table 9-11. overriding signals for alternate functions in pc3.. pc0 signal name pc3/a11 pc2/a10 pc1/a9 pc0/a8 puoe sre ? (xmm < 5) sre ? (xmm < 6) sre ? (xmm < 7) sre ? (xmm < 7) puov 0 0 0 0 ddoe sre ? (xmm < 5) sre ? (xmm < 6) sre ? (xmm < 7) sre ? (xmm < 7) ddov 1 1 1 1 pvoe sre ? (xmm < 5) sre ? (xmm < 6) sre ? (xmm < 7) sre ? (xmm < 7) pvov a11 a10 a9 a8 ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio ? ? ? ? table 9-12. port d pins alternate functions port pin alternate function pd7 t0 (timer/counter0 clock input) pd6 rxcan/t1 (can receive pin or timer/counter1 cloc k input) pd5 txcan/xck1 (can transmit pin or usart1 external clock input/output) pd4 icp1 (timer/counter1 input capture trigger) pd3 int3/txd1 (external interrupt3 input or uart1 tr ansmit pin) pd2 int2/rxd1 (external interrupt2 input or uart1 re ceive pin) pd1 int1/sda (external interrupt1 input or twi seria l data) pd0 int0/scl (external interrupt0 input or twi seria l clock)
81 7682c?auto?04/08 at90can32/64/128 txcan, can transmit data (data output pin for the c an). when the can is enabled, this pin is configured as an output regardless of the value of ddd5. xck1, usart1 external clock. the data direction reg ister (ddd5) controls whether the clock is output (ddd5 set) or input (ddd45 cleared). the xck1 pin is active only when the usart1 operates in synchronous mode. ? icp1 ? port d, bit 4 icp1, input capture pin1. the pd4 pin can act as an input capture pin for timer/counter1. ? int3/txd1 ? port d, bit 3 int3, external interrupt source 3. the pd3 pin can serve as an external interrupt source to the mcu. txd1, transmit data (data output pin for the usart1 ). when the usart1 transmitter is enabled, this pin is configured as an output regard less of the value of ddd3. ? int2/rxd1 ? port d, bit 2 int2, external interrupt source 2. the pd2 pin can serve as an external interrupt source to the mcu. rxd1, receive data (data input pin for the usart1). when the usart1 receiver is enabled this pin is configured as an input regardless of th e value of ddd2. when the usart forces this pin to be an input, the pull-up can still be contro lled by the portd2 bit. ? int1/sda ? port d, bit 1 int1, external interrupt source 1. the pd1 pin can serve as an external interrupt source to the mcu. sda, two-wire serial interface data. when the twen bit in twcr is set (one) to enable the two-wire serial interface, pin pd1 is disconnected from the port and becomes the serial data i/o pin for the two-wire serial interface. in this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal , and the pin is driven by an open drain driver with slew-rate limitation. ? int0/scl ? port d, bit 0 int0, external interrupt source 0. the pd0 pin can serve as an external interrupt source to the mcu. scl, two-wire serial interface clock: when the twen bit in twcr is set (one) to enable the two-wire serial interface, pin pd0 is disconnected from the port and becomes the serial clock i/o pin for the two-wire serial interface. in this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal , and the pin is driven by an open drain driver with slew-rate limitation.
82 7682c?auto?04/08 at90can32/64/128 table 9-13 and table 9-14 relates the alternate functions of port d to the o verriding signals shown in figure 9-5 on page 72 . note: 1. when enabled, the two-wire serial interface enables slew-rate controls on the output pins pd0 and pd1. this is not shown in this table. in ad dition, spike filters are connected between the aio outputs shown in the port figure and the di gital logic of the twi module. table 9-13. overriding signals for alternate functions pd7..pd4 signal name pd7/t0 pd6/t1/rxcan pd5/xck1/txcan pd4/icp1 puoe 0 rxcanen txcanen + 0 puov 0 portd6 ? pud 0 0 ddoe 0 rxcanen txcanen 0 ddov 0 0 1 0 pvoe 0 0 txcanen + umsel1 0 pvov 0 0 (xck1 output ? umsel1 ? txcanen ) + (txcan ? txcanen) 0 ptoe 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di t0 input t1 input/rxcan xck1 input icp1 input aio ? ? ? ? table 9-14. overriding signals for alternate functions in pd3.. pd0 (1) signal name pd3/int3/txd1 pd2/int2/rxd1 pd1/int1/sda pd 0/int0/scl puoe txen1 rxen1 twen twen puov 0 portd2 ? pud portd1 ? pud portd0 ? pud ddoe txen1 rxen1 0 0 ddov 1 0 0 0 pvoe txen1 0 twen twen pvov txd1 0 sda_out scl_out ptoe 0 0 0 0 dieoe int3 enable int2 enable int1 enable int0 enable dieov int3 enable int2 enable int1 enable int0 enable di int3 input int2 input/rxd1 int1 input int0 input aio ? ? sda input scl input
83 7682c?auto?04/08 at90can32/64/128 9.3.6 alternate functions of port e the port e pins with alternate functions are shown in table 9-15 . the alternate pin configuration is as follows: ? pcint7/icp3 ? port e, bit 7 int7, external interrupt source 7. the pe7 pin can serve as an external interrupt source. icp3, input capture pin3: the pe7 pin can act as an input capture pin for timer/counter3. ? int6/t3 ? port e, bit 6 int6, external interrupt source 6. the pe6 pin can serve as an external interrupt source. t3, timer/counter3 counter source. ? int5/oc3c ? port e, bit 5 int5, external interrupt source 5. the pe5 pin can serve as an external interrupt source. oc3c, output compare match c output. the pe5 pin ca n serve as an external output for the timer/counter3 output compare c. the pin has to be configured as an output (dde5 set ?one?) to serve this function. the oc3c pin is also the ou tput pin for the pwm mode timer function. ? int4/oc3b ? port e, bit 4 int4, external interrupt source 4. the pe4 pin can serve as an external interrupt source. oc3b, output compare match b output. the pe4 pin ca n serve as an external output for the timer/counter3 output compare b. the pin has to be configured as an output (dde4 set (one)) to serve this function. the oc3b pin is also the ou tput pin for the pwm mode timer function. ? ain1/oc3a ? port e, bit 3 ain1 ? analog comparator negative input. this pin i s directly connected to the negative input of the analog comparator. oc3a, output compare match a output. the pe3 pin ca n serve as an external output for the timer/counter3 output compare a. the pin has to be configured as an output (dde3 set ?one?) to serve this function. the oc3a pin is also the ou tput pin for the pwm mode timer function. table 9-15. port e pins alternate functions port pin alternate function pe7 int7/icp3 (external interrupt 7 input or timer/c ounter3 input capture trigger) pe6 int6/ t3 (external interrupt 6 input or timer/co unter3 clock input) pe5 int5/oc3c (external interrupt 5 input or output com pare and pwm output c for timer/counter3) pe4 int4/oc3b (external interrupt4 input or output comp are and pwm output b for timer/counter3) pe3 ain1/oc3a (analog comparator negative input or outp ut compare and pwm output a for timer/counter3) pe2 ain0/xck0 (analog comparator positive input or u sart0 external clock input/output) pe1 pdo/txd0 (programming data output or uart0 trans mit pin) pe0 pdi/rxd0 (programming data input or uart0 receiv e pin)
84 7682c?auto?04/08 at90can32/64/128 ? ain0/xck0 ? port e, bit 2 ain0 ? analog comparator positive input. this pin i s directly connected to the positive input of the analog comparator. xck0, usart0 external clock. the data direction reg ister (dde2) controls whether the clock is output (dde2 set) or input (dde2 cleared). the x ck0 pin is active only when the usart0 operates in synchronous mode. ? pdo/txd0 ? port e, bit 1 pdo, spi serial programming data output. during ser ial program downloading, this pin is used as data output line for the at90can32/64/128. txd0, uart0 transmit pin. ? pdi/rxd0 ? port e, bit 0 pdi, spi serial programming data input. during seri al program downloading, this pin is used as data input line for the at90can32/64/128. rxd0, usart0 receive pin. receive data (data input pin for the usart0). when the usart0 receiver is enabled this pin is configured a s an input regardless of the value of ddre0. when the usart0 forces this pin to be an input, a l ogical one in porte0 will turn on the inter- nal pull-up. table 9-16 and table 9-17 relates the alternate functions of port e to the o verriding signals shown in figure 9-5 on page 72 . table 9-16. overriding signals for alternate functions pe7..pe4 signal name pe7/int7/icp3 pe6/int6/t3 pe5/int5/oc3c pe4 /int4/oc3b puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 oc3c enable oc3b enable pvov 0 0 oc3c oc3b ptoe 0 0 0 0 dieoe int7 enable int6 enable int5 enable int4 enable dieov int7 enable int6 enable int5 enable int4 enable di int7 input /icp3 input int6 input /t3 input int5 input int4 input aio ? ? ? ?
85 7682c?auto?04/08 at90can32/64/128 note: 1. ain0d and ain1d is described in ?digital input disable register 1 ? didr1? on page 271 . 9.3.7 alternate functions of port f the port f has an alternate function as analog inpu t for the adc as shown in table 9-18 . if some port f pins are configured as outputs, it is e ssential that these do not switch when a con- version is in progress. this might corrupt the resu lt of the conversion. if the jtag interface is enabled, the pull-up resistors on pins pf7 (tdi), p f5 (tms) and pf4 (tck) will be activated even if a reset occurs. the alternate pin configuration is as follows: ? tdi, adc7 ? port f, bit 7 adc7, analog to digital converter, input channel 7 . table 9-17. overriding signals for alternate functions in pe3.. pe0 signal name pe3/ain1/oc3a pe2/ain0/xck0 pe1/pdo/txd0 pe 0/pdi/rxd0 puoe 0 0 txen0 rxen0 puov 0 0 0 porte0 ? pud ddoe 0 0 txen0 rxen0 ddov 0 0 1 0 pvoe oc3a enable umsel0 txen0 0 pvov oc3a xck0 output txd0 0 ptoe 0 0 0 0 dieoe ain1d (1) ain0d (1) 0 0 dieov 0 0 0 0 di 0 xck0 input ? rxd0 aio ain1 input ain0 input ? ? table 9-18. port f pins alternate functions port pin alternate function pf7 adc7/tdi (adc input channel 7 or jtag data input ) pf6 adc6/tdo (adc input channel 6 or jtag data outpu t) pf5 adc5/tms (adc input channel 5 or jtag mode selec t) pf4 adc4/tck (adc input channel 4 or jtag clock) pf3 adc3 (adc input channel 3) pf2 adc2 (adc input channel 2) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0)
86 7682c?auto?04/08 at90can32/64/128 tdi, jtag test data in. serial input data to be shi fted in to the instruction register or data reg- ister (scan chains). when the jtag interface is ena bled, this pin can not be used as an i/o pin. ? tck, adc6 ? port f, bit 6 adc6, analog to digital converter, input channel 6 . tdo, jtag test data out. serial output data from in struction register or data register. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tms, adc5 ? port f, bit 5 adc5, analog to digital converter, input channel 5 . tms, jtag test mode select. this pin is used for na vigating through the tap-controller state machine. when the jtag interface is enabled, this p in can not be used as an i/o pin. ? tdo, adc4 ? port f, bit 4 adc4, analog to digital converter, input channel 4 . tck, jtag test clock. jtag operation is synchronous to tck. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? adc3 ? port f, bit 3 adc3, analog to digital converter, input channel 3. ? adc2 ? port f, bit 2 adc2, analog to digital converter, input channel 2. ? adc1 ? port f, bit 1 adc1, analog to digital converter, input channel 1. ? adc0 ? port f, bit 0 adc0, analog to digital converter, input channel 0.
87 7682c?auto?04/08 at90can32/64/128 table 9-19 and table 9-20 relates the alternate functions of port f to the o verriding signals shown in figure 9-5 on page 72 . table 9-19. overriding signals for alternate functions in pf7.. pf4 signal name pf7/adc7/tdi pf6/adc6/tdo pf5/adc5/tms pf4/ adc4/tck puoe jtagen jtagen jtagen jtagen puov jtagen jtagen jtagen jtagen ddoe jtagen jtagen jtagen jtagen ddov 0 shift_ir + shift_dr 0 0 pvoe jtagen jtagen jtagen jtagen pvov 0 tdo 0 0 ptoe 0 0 0 0 dieoe jtagen + adc7d jtagen + adc6d jtagen + adc5d jtagen + adc4d dieov jtagen 0 jtagen jtagen di tdi ? tms tck aio adc7 input adc6 input adc5 input adc4 input table 9-20. overriding signals for alternate functions in pf3.. pf0 signal name pf3/adc3 pf2/adc2 pf1/adc1 pf0/adc0 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 ptoe 0 0 0 0 dieoe adc3d adc2d adc1d adc0d dieov 0 0 0 0 di ? ? ? ? aio adc3 input adc2 input adc1 input adc0 input
88 7682c?auto?04/08 at90can32/64/128 9.3.8 alternate functions of port g the alternate pin configuration is as follows: the alternate pin configuration is as follows: ? tosc1 ? port g, bit 4 tosc2, timer/counter2 oscillator pin 1. when the as 2 bit in assr is set (one) to enable asyn- chronous clocking of timer/counter2, pin pg4 is dis connected from the port, and becomes the input of the inverting oscillator amplifier. in thi s mode, a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. ? tosc2 ? port g, bit 3 tosc2, timer/counter2 oscillator pin 2. when the as 2 bit in assr is set (one) to enable asyn- chronous clocking of timer/counter2, pin pg3 is dis connected from the port, and becomes the inverting output of the oscillator amplifier. in th is mode, a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. ? ale ? port g, bit 2 ale is the external data memory address latch enabl e signal. ? rd ? port g, bit 1 rd is the external data memory read control strobe. ? wr ? port g, bit 0 wr is the external data memory write control strobe. table 9-21. port g pins alternate functions port pin alternate function pg4 tosc1 (rtc oscillator timer/counter2) pg3 tosc2 (rtc oscillator timer/counter2) pg2 ale (address latch enable to external memory) pg1 rd (read strobe to external memory) pg0 wr (write strobe to external memory)
89 7682c?auto?04/08 at90can32/64/128 table 9-21 and table 9-22 relates the alternate functions of port g to the o verriding signals shown in figure 9-5 on page 72 . 9.4 register description for i/o-ports 9.4.1 port a data register ? porta table 9-22. overriding signals for alternate function in pg4 signal name - - - pg4/tosc1 puoe as2 puov 0 ddoe as2 ddov 0 pvoe 0 pvov 0 ptoe 0 dieoe as2 dieov exclk di ? aio t/c2 osc input table 9-23. overriding signals for alternate functions in pg3:0 signal name pg3/tosc2 pg2/ale pg1/rd pg0/wr puoe as2 ? exclk sre sre sre puov 0 0 0 0 ddoe as2 ? exclk sre sre sre ddov 0 1 1 1 pvoe 0 sre sre sre pvov 0 ale rd wr ptoe 0 0 0 0 dieoe as2 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio t/c2 osc output ? ? ? bit 7 6 5 4 3 2 1 0 porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 por ta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
90 7682c?auto?04/08 at90can32/64/128 9.4.2 port a data direction register ? ddra 9.4.3 port a input pins address ? pina 9.4.4 port b data register ? portb 9.4.5 port b data direction register ? ddrb 9.4.6 port b input pins address ? pinb 9.4.7 port c data register ? portc 9.4.8 port c data direction register ? ddrc 9.4.9 port c input pins address ? pinc bit 7 6 5 4 3 2 1 0 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 7 6 5 4 3 2 1 0 portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 por tb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 7 6 5 4 3 2 1 0 portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 por tc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a
91 7682c?auto?04/08 at90can32/64/128 9.4.10 port d data register ? portd 9.4.11 port d data direction register ? ddrd 9.4.12 port d input pins address ? pind 9.4.13 port e data register ? porte 9.4.14 port e data direction register ? ddre 9.4.15 port e input pins address ? pine 9.4.16 port f data register ? portf 9.4.17 port f data direction register ? ddrf bit 7 6 5 4 3 2 1 0 portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 por td read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 7 6 5 4 3 2 1 0 porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 por te read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 7 6 5 4 3 2 1 0 portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 por tf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
92 7682c?auto?04/08 at90can32/64/128 9.4.18 port f input pins address ? pinf 9.4.19 port g data register ? portg 9.4.20 port g data direction register ? ddrg 9.4.21 port g input pins address ? ping bit 7 6 5 4 3 2 1 0 pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 pinf read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 7 6 5 4 3 2 1 0 ? ? ? portg4 portg3 portg2 portg1 portg0 portg read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 ddrg read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? ? ping4 ping3 ping2 ping1 ping0 ping read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 n/a n/a n/a n/a n/a
93 7682c?auto?04/08 at90can32/64/128 10. external interrupts the external interrupts are triggered by the int7:0 pins. observe that, if enabled, the interrupts will trigger even if the int7:0 pins are configured as outputs. this feature provides a way of gen- erating a software interrupt. the external interrup ts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the spe cification for the external interrupt control reg- isters ? eicra (int3:0) and eicrb (int7:4). when th e external interrupt is enabled and is configured as level triggered, the interrupt will t rigger as long as the pin is held low. note that recognition of falling or rising edge interrupts on int7:4 requires the presence of an i/o clock, described in ?clock systems and their distribution? on page 37 . low level interrupts and the edge interrupt on int3:0 are detected asynchronousl y. this implies that these interrupts can be used for waking the part also from sleep modes othe r than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used fo r wake-up from power-down mode, the changed level must be held for some time to wake up the mcu . this makes the mcu less sensitive to noise. the changed level is sampled twice by the wa tchdog oscillator clock. the period of the watchdog oscillator is 1 s (nominal) at 5.0v and 2 5 c. the frequency of the watchdog oscilla- tor is voltage dependent as shown in the ?electrical characteristics (1)? on page 364 . the mcu will wake up if the input has the required level du ring this sampling or if it is held until the end o f the start-up time. the start-up time is defined by the sut fuses as described in ?system clock? on page 37 . if the level is sampled twice by the watchdog osc illator clock but disappears before the end of the start-up time, the mcu will still wa ke up, but no interrupt will be generated. the required level must be held long enough for the mcu to complete the wake up to trigger the level interrupt. 10.0.1 asynchronous external interrupt control regis ter a ? eicra ? bits 7..0 ? isc31, isc30 ? isc01, isc00: asynchron ous external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are activated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. t he level and edges on the external pins that activate the interrupts are defined in table 10-1 . edges on int3..int0 are registered asynchro- nously. pulses on int3:0 pins wider than the minimu m pulse width given in table 10-2 will generate an interrupt. shorter pulses are not guara nteed to generate an interrupt. if low level interrupt is selected, the low level must be held u ntil the completion of the currently executing instruction to generate an interrupt. if enabled, a level triggered interrupt will generate an inter- rupt request as long as the pin is held low. when c hanging the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing its interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finally, the intn interrupt flag should be cleared by writing a logical one to its interrupt f lag bit (intfn) in the eifr register before the interrupt is re-enabled. bit 7 6 5 4 3 2 1 0 isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
94 7682c?auto?04/08 at90can32/64/128 note: 1. n = 3, 2, 1 or 0. when changing the iscn1/iscn0 bits, the interrupt m ust be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an inte rrupt can occur when the bits are changed. 10.0.2 synchronous external interrupt control regist er b ? eicrb ? bits 7..0 ? isc71, isc70 - isc41, isc40: synchrono us external interrupt 7 - 4 sense control bits the external interrupts 7 - 4 are activated by the external pins int7:4 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. t he level and edges on the external pins that activate the interrupts are defined in table 10-3 . the value on the int7:4 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. shorter pu lses are not guaranteed to generate an inter- rupt. observe that cpu clock frequency can be lower than the xtal frequency if the xtal divider is enabled. if low level interrupt is selec ted, the low level must be held until the comple- tion of the currently executing instruction to gene rate an interrupt. if enabled, a level triggered interrupt will generate an interrupt request as lon g as the pin is held low. note: 1. n = 7, 6, 5 or 4. when changing the iscn1/iscn0 bits, the interrupt m ust be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an inte rrupt can occur when the bits are changed. table 10-1. asynchronous external interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt requ est. 0 1 any logical change on intn generates an interrupt request 1 0 the falling edge of intn generates asynchronously an interrupt request. 1 1 the rising edge of intn generates asynchronously an interrupt request. table 10-2. asynchronous external interrupt characteristics symbol parameter condition min typ max units t int minimum pulse width for asynchronous external interrupt 50 ns bit 7 6 5 4 3 2 1 0 isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 eicrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 10-3. synchronous external interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt requ est. 0 1 any logical change on intn generates an interrupt request 1 0 the falling edge between two samples of intn gene rates an interrupt request. 1 1 the rising edge between two samples of intn gener ates an interrupt request.
95 7682c?auto?04/08 at90can32/64/128 10.0.3 external interrupt mask register ? eimsk ? bits 7..0 ? int7 ? int0: external interrupt reques t 7 - 0 enable when an int7 ? int0 bit is written to one and the i -bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control registers ? eicra and ei crb ? defines whether the external inter- rupt is activated on rising or falling edge or leve l sensed. activity on any of these pins will trigge r an interrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. 10.0.4 external interrupt flag register ? eifr ? bits 7..0 ? intf7 - intf0: external interrupt flag s 7 - 0 when an edge or logic change on the int7:0 pin trig gers an interrupt request, intf7:0 becomes set (one). if the i-bit in sreg and the correspondi ng interrupt enable bit, int7:0 in eimsk, are set (one), the mcu will jump to the interrupt vecto r. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int7:0 are configured as level interrupt. note that when entering sleep mode with the int3:0 interrupts disabled, the input buffers on these pins will be disabled. this may cause a logic change in internal signals which will set the intf3:0 flags. see ?digital input enable and sleep modes? on page 70 for more information. bit 7 6 5 4 3 2 1 0 int7 int6 int5 int4 int3 int2 int1 iint0 eimsk read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 intf7 intf6 intf5 intf4 intf3 intf2 intf1 iintf0 eifr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
96 7682c?auto?04/08 at90can32/64/128 11. timer/counter3/1/0 prescalers timer/counter3, timer/counter1 and timer/counter0 s hare the same prescaler module, but the timer/counters can have different prescaler setting s. the description below applies to both timer/counter3, timer/counter1 and timer/counter0. 11.1 overview most bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number. 11.1.1 internal clock source the timer/counter can be clocked directly by the sy stem clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum time r/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescal er can be used as a clock source. the prescaled clock has a frequency o f either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 11.1.2 prescaler reset the prescaler is free running, i.e., operates indep endently of the clock select logic of the timer/counter, and it is shared by timer/counter3, timer/counter1 and timer/counter0. since the prescaler is not affected by the timer/counter? s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. one example of prescaling arti- facts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer i s enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals t he prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synch ronizing the timer/counter to program execu- tion. however, care must be taken if the other time r/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/counters it is connected to. 11.1.3 external clock source an external clock source applied to the t3/t1/t0 pi n can be used as timer/counter clock (clk t3 /clk t1 /clk t0 ). the t3/t1/t0 pin is sampled once every system cl ock cycle by the pin syn- chronization logic. the synchronized (sampled) sign al is then passed through the edge detector. figure 11-1 shows a functional equivalent block diagram of the t3/t1/t0 synchronization and edge detector logic. the registers are clocked at t he positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of t he internal system clock. the edge detector generates one clk t3 /clk t1 /clk t0 pulse for each positive (csn2:0 = 7) or nega- tive (csn2:0 = 6) edge it detects.
97 7682c?auto?04/08 at90can32/64/128 figure 11-1. t3/t1/t0 pin sampling the synchronization and edge detector logic introdu ces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t3/t1/t0 pin t o the counter is updated. enabling and disabling of the clock input must be d one when t3/t1/t0 has been stable for at least one system clock cycle, otherwise it is a ris k that a false timer/counter clock pulse is generated. each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50 % duty cycle. since the edge dete ctor uses sampling, the maximum frequency of an external cloc k it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal , resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external c lock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 11-2. prescaler for timer/counter3, timer/counter1 and ti mer/counter0 (1) note: 1. the synchronization logic on the input pins ( t0/t1/t3) is shown in figure 11-1 . tn_sync (to clock select logi edge detector synchronization d q d q le d q tn clk i/o psr310 clear 10-bit t/c prescaler ck ck/8 ck/64 ck/256 ck/1024 clk t1 timer/counter1 clock source 0 cs10 cs11 cs12 t1 clk t3 timer/counter3 clock source 0 cs30 cs31 cs32 t3 clk t0 timer/counter0 clock source 0 cs00 cs01 cs02 t0 synchronization synchronization synchronization
98 7682c?auto?04/08 at90can32/64/128 11.2 timer/counter0/1/3 prescalers register descript ion 11.2.1 general timer/counter control register ? gtcc r ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/coun ter synchronization mode. in this mode, the value that is written to the psr2 and psr310 bits i s kept, hence keeping the corresponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during con- figuration. when the tsm bit is written to zero, th e psr2 and psr310 bits are cleared by hardware, and the timer/counters start counting sim ultaneously. ? bit 0 ? psr310: prescaler reset timer/counter3, ti mer/counter1 and timer/counter0 when this bit is one, timer/counter3, timer/counter 1 and timer/counter0 prescaler will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is set. note that timer/counter3, timer/counter1 and timer/count er0 share the same prescaler and a reset of this prescaler will affect these three timers. bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ? psr2 psr310 gtccr read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0
99 7682c?auto?04/08 at90can32/64/128 12. 8-bit timer/counter0 with pwm timer/counter0 is a general purpose, single channel , 8-bit timer/counter module. the main features are: 12.1 features ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (p wm) ? frequency generator ? external event counter ? 10-bit clock prescaler ? overflow and compare match interrupt sources (tov0 and ocf0a) 12.2 overview many register and bit references in this section ar e written in general form. ? a lower case ?n? replaces the timer/counter number , in this case 0. however, when using the register or bit defines in a program, the preci se form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr0a for accessing timer/counter0 output compare channel a v alue and so on. a simplified block diagram of the 8-bit timer/count er is shown in figure 12-1 . for the actual placement of i/o pins, refer to ?pinout at90can32/64/128 - tqfp? on page 5 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 109 . figure 12-1. 8-bit timer/counter block diagram timer/counter data bus = tcntn waveform generation ocnx = 0 control logic = 0xff bottom count clear direction tovn (int.req.) ocrnx tccrn clock select tn edge detector ( from prescaler ) clk tn top ocn (int.req.)
100 7682c?auto?04/08 at90can32/64/128 12.2.1 registers the timer/counter (tcnt0) and output compare regist er (ocr0a) are 8-bit registers. inter- rupt request (abbreviated to int.req. in the figure ) signals are all visible in the timer interrupt flag register (tifr0). all interrupts are individua lly masked with the timer interrupt mask reg- ister (timsk0). tifr0 and timsk0 are not shown in t he figure. the timer/counter can be clocked internally, via th e prescaler, or by an external clock source on the t0 pin. the clock select logic block controls w hich clock source and edge the timer/counter uses to increment (or decrement) its value. the tim er/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare register (ocr0a) is compared with the timer/counter value at all times. the result of the compare can b e used by the waveform generator to gener- ate a pwm or variable frequency output on the outpu t compare pin (oc0a). see ?output compare unit? on page 101. for details. the compare match event will also set the compare flag (ocf0a) which can be used to generate an outpu t compare interrupt request. 12.2.2 definitions the following definitions are used extensively thro ughout the section: 12.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is cont rolled by the clock select (cs02:0) bits located in the timer/counter control register (tccr 0a). for details on clock sources and pres- caler, see ?timer/counter3/1/0 prescalers? on page 96 . 12.4 counter unit the main part of the 8-bit timer/counter is the pro grammable bi-directional counter unit. figure 12-2 shows a block diagram of the counter and its surro undings. figure 12-2. counter unit block diagram bottom the counter reaches the bottom when it become s 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equa l to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. th e assignment is depen- dent on the mode of operation. data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn bottom direction clear
101 7682c?auto?04/08 at90can32/64/128 signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has reached minimum value (zer o). depending of the mode of operation used, the counte r is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal cloc k source, selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be a ccessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has prio rity over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a). there are close connections between how the counter behaves (counts) and how waveforms are gene rated on the output compare output oc0a. for more details about advanced counting sequ ences and waveform generation, see ?modes of operation? on page 104 . the timer/counter overflow flag (tov0) is set accor ding to the mode of operation selected by the wgm01:0 bits. tov0 can be used for generating a cpu interrupt. 12.5 output compare unit the 8-bit comparator continuously compares tcnt0 wi th the output compare register (ocr0a). whenever tcnt0 equals ocr0a, the comparato r signals a match. a match will set the output compare flag (ocf0a) at the next timer c lock cycle. if enabled (ocie0a = 1 and global interrupt flag in sreg is set), the output c ompare flag generates an output compare interrupt. the ocf0a flag is automatically cleared when the interrupt is executed. alternatively, the ocf0a flag can be cleared by software by writin g a logical one to its i/o bit location. the waveform generator uses the match signal to generat e an output according to operating mode set by the wgm01:0 bits and compare output mode (co m0a1:0) bits. the max and bottom sig- nals are used by the waveform generator for handlin g the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 104. ).
102 7682c?auto?04/08 at90can32/64/128 figure 12-3 shows a block diagram of the output compare unit. figure 12-3. output compare unit, block diagram the ocr0a register is double buffered when using an y of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (c tc) modes of operation, the double buff- ering is disabled. the double buffering synchronize s the update of the ocr0a compare register to either top or bottom of the counting se quence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulse s, thereby making the output glitch-free. the ocr0a register access may seem complex, but thi s is not case. when the double buffer- ing is enabled, the cpu has access to the ocr0a buf fer register, and if double buffering is disabled the cpu will access the ocr0a directly. 12.5.1 force output compare in non-pwm waveform generation modes, the match out put of the comparator can be forced by writing a one to the force output compare (foc0a) b it. forcing compare match will not set the ocf0a flag or reload/clear the timer, but the oc0a pin will be updated as if a real compare match had occurred (the com0a1:0 bits settings defi ne whether the oc0a pin is set, cleared or toggled). 12.5.2 compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any compare match that occur in the next timer clock cycle, even when the timer is stop ped. this feature allows ocr0a to be initial- ized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 12.5.3 using the output compare unit since writing tcnt0 in any mode of operation will b lock all compare matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare channel, independently of whether the timer/counter is runni ng or not. if the value written to tcnt0 equals the ocr0a value, the compare match will be m issed, resulting in incorrect waveform ocfn x (int.req. = (8-bit comparator ) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom
103 7682c?auto?04/08 at90can32/64/128 generation. similarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0a should be performed before se tting the data direction register for the port pin to output. the easiest way of setting the oc0a value is to use the force output com- pare (foc0a) strobe bits in normal mode. the oc0a r egister keeps its value even when changing between waveform generation modes. be aware that the com0a1:0 bits are not double buff ered together with the compare value. changing the com0a1:0 bits will take effect immedia tely. 12.6 compare match output unit the compare output mode (com0a1:0) bits have two fu nctions. the waveform generator uses the com0a1:0 bits for defining the output comp are (oc0a) state at the next compare match. also, the com0a1:0 bits control the oc0a pin output source. figure 12-4 shows a sim- plified schematic of the logic affected by the com0 a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control regis- ters (ddr and port) that are affected by the com0a1 :0 bits are shown. when referring to the oc0a state, the reference is for the internal oc0a register, not the oc0a pin. if a system reset occur, the oc0a register is reset to ?0?. figure 12-4. compare match output unit, schematic 12.6.1 compare output function the general i/o port function is overridden by the output compare (oc0a) from the waveform generator if either of the com0a1:0 bits are set. h owever, the oc0a pin direction (input or out- put) is still controlled by the data direction regi ster (ddr) for the port pin. the data direction register bit for the oc0a pin (ddr_oc0a) must be se t as output before the oc0a value is vis- ible on the pin. the port override function is inde pendent of the waveform generation mode. the design of the output compare pin logic allows i nitialization of the oc0a state before the output is enabled. note that some com0a1:0 bit sett ings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on p age 109. port ddr d q d q ocnx pin ocnx d q waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o
104 7682c?auto?04/08 at90can32/64/128 12.6.2 compare output mode and waveform generation the waveform generator uses the com0a1:0 bits diffe rently in normal, ctc, and pwm modes. for all modes, setting the com0a1:0 = 0 tell s the waveform generator that no action on the oc0a register is to be performed on the next co mpare match. for compare output actions in the non-pwm modes refer to table 12-2 on page 110 . for fast pwm mode, refer to table 12- 3 on page 110 , and for phase correct pwm refer to table 12-4 on page 111 . a change of the com0a1:0 bits state will have effec t at the first compare match after the bits are written. for non-pwm modes, the action can be force d to have immediate effect by using the foc0a strobe bits. 12.7 modes of operation the mode of operation, i.e., the behavior of the ti mer/counter and the output compare pins, is defined by the combination of the waveform generati on mode (wgm01:0) and compare output mode (com0a1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com 0a1:0 bits control whether the pwm output generated should be inverted or not (inverte d or non-inverted pwm). for non-pwm modes the com0a1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 103. ). for detailed timing information refer to figure 12-8 , figure 12-9 , figure 12-10 and figure 12-11 in ?timer/counter timing diagrams? on page 108 . 12.7.1 normal mode the simplest mode of operation is the normal mode ( wgm01:0 = 0). in this mode the counting direction is always up (incrementing), and no count er clear is performed. the counter simply overruns when it passes its maximum 8-bit value (to p = 0xff) and then restarts from the bot- tom (0x00). in normal operation the timer/counter o verflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the to v0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. howev er, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode , a new counter value can be written anytime. the output compare unit can be used to generate int errupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 12.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm01:0 = 2) , the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater contr ol of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 12-5 . the counter value (tcnt0) increases until a compare match occurs between tcnt 0 and ocr0a, and then counter (tcnt0) is cleared.
105 7682c?auto?04/08 at90can32/64/128 figure 12-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interr upt handler routine can be used for updating the top value. however, changing top to a value close t o bottom when the counter is running with none or a low prescaler value must be done wit h care since the ctc mode does not have the double buffering feature. if the new value writ ten to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the counter will then have to count to its max- imum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the o c0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated wi ll have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform f requency is defined by the following equation: the n variable represents the prescale factor (1, 8 , 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 12.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (w gm01:0 = 3) provides a high frequency pwm waveform generation option. the fast pwm differ s from the other pwm option by its sin- gle-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compa re (oc0a) is cleared on the compare match between tcnt0 and ocr0a, and set at bottom. i n inverting compare output mode, the output is set on compare match and cleared at b ottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequ ency makes the fast pwm mode well suited for power regulation, rectification, and dac applic ations. high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 12-6 . the tcnt0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and tcntn ocnx (toggle) ocnx interrupt flag s 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + ( ) -------------------------------------------------- =
106 7682c?auto?04/08 at90can32/64/128 inverted pwm outputs. the small horizontal line mar ks on the tcnt0 slopes represent compare matches between ocr0a and tcnt0. figure 12-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches max. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generatio n of pwm waveforms on the oc0a pin. setting the com0a1:0 bits to two will produce a non -inverted pwm and an inverted pwm output can be generated by setting the com0a1:0 to three ( see table 12-3 on page 110 ). the actual oc0a value will only be visible on the port pin if the data direction for the port pin is set as out- put. the pwm waveform is generated by setting (or c learing) the oc0a register at the compare match between ocr0a and tcnt0, and clearing (or set ting) the oc0a register at the timer clock cycle the counter is cleared (changes from ma x to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8 , 64, 256, or 1024). the extreme values for the ocr0a register represent s special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on th e polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output i n fast pwm mode can be achieved by set- ting oc0a to toggle its logical level on each compa re match (com0a1:0 = 1). the waveform generated will have a maximum frequency of f oc0a = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the out- put compare unit is enabled in the fast pwm mode. tcntn ocrnx update and tovn interrupt flag s 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ?????????????????? =
107 7682c?auto?04/08 at90can32/64/128 12.7.4 phase correct pwm mode the phase correct pwm mode (wgm01:0 = 1) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm m ode is based on a dual-slope operation. the counter counts repeatedly from bottom to max an d then from max to bottom. in non- inverting compare output mode, the output compare ( oc0a) is cleared on the compare match between tcnt0 and ocr0a while upcounting, and set o n the compare match while down- counting. in inverting output compare mode, the ope ration is inverted. the dual-slope operation has lower maximum operation frequency than single s lope operation. however, due to the sym- metric feature of the dual-slope pwm modes, these m odes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode i s fixed to eight bits. in phase correct pwm mode the counter is incremented until the count er value matches max. when the counter reaches max, it changes the count direction. the tc nt0 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 12-7 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and in verted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare ma tches between ocr0a and tcnt0. figure 12-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0a pin. setting the com0a1:0 bits to two will pro duce a non-inverted pwm. an inverted pwm output can be generated by setting the com0a1:0 to three (see table 12-4 on page 111 ). the actual oc0a value will only be visible on the p ort pin if the data direction for the port pin is set as output. the pwm waveform is generated by cle aring (or setting) the oc0a register at the compare match between ocr0a and tcnt0 when the coun ter increments, and setting (or clearing) the oc0a register at compare match betwee n ocr0a and tcnt0 when the counter tovn interrupt flag s ocnx interrupt flag s 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update
108 7682c?auto?04/08 at90can32/64/128 decrements. the pwm frequency for the output when u sing phase correct pwm can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8 , 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if t he ocr0a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. 12.8 timer/counter timing diagrams the timer/counter is a synchronous design and the t imer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the f igures include information on when interrupt flags are set. figure 12-8 contains timing data for basic timer/counter opera tion. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 12-8. timer/counter timing diagram, no prescaling figure 12-9 shows the same timing data, but with the prescaler enabled. figure 12-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) f ocnxpcpwm f clk_i/o n 510 ? ------------------ = clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8)
109 7682c?auto?04/08 at90can32/64/128 figure 12-10 shows the setting of ocf0a in all modes except ctc mode. figure 12-10. timer/counter timing diagram, setting of ocf0a, wit h prescaler (f clk_i/o /8) figure 12-11 shows the setting of ocf0a and the clearing of tcn t0 in ctc mode. figure 12-11. timer/counter timing diagram, clear timer on compar e match mode, with pres- caler (f clk_i/o /8) 12.9 8-bit timer/counter register description 12.9.1 timer/counter0 control register a ? tccr0a ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm00 bit spe cifies a non-pwm mode. however, for ensuring compatibility with future devices, this bi t must be set to zero when tccr0a is written when operating in pwm mode. when writing a logical one to the foc0a bit, an immediate com- pare match is forced on the waveform generation uni t. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a b it is implemented as a strobe. therefore it is the value present in the com0a1:0 bits that determi nes the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 tccr0a read/write w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
110 7682c?auto?04/08 at90can32/64/128 ? bit 6, 3 ? wgm01:0: waveform generation mode these bits control the counting sequence of the cou nter, the source for the maximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode, clear t imer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes. se e table 12-1 and ?modes of operation? on page 104 . note: 1. the ctc0 and pwm0 bit definition names are n ow obsolete. use the wgm01:0 definitions. however, the functionality and location of these bi ts are compatible with previous versions of the timer. ? bit 5:4 ? com01:0: compare match output mode these bits control the output compare pin (oc0a) be havior. if one or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm01:0 bit setting. table 12-2 shows the com0a1:0 bit functionality when the wgm0 1:0 bits are set to a normal or ctc mode (non-pwm). table 12-3 shows the com0a1:0 bit functionality when the wgm0 1:0 bits are set to fast pwm mode. table 12-1. waveform generation mode bit description (1) mode wgm01 (ctc0) wgm00 (pwm0) timer/counter mode of operation top update of ocr0a at tov0 flag set on 0 0 0 normal 0xff immediate max 1 0 1 pwm, phase correct 0xff top bottom 2 1 0 ctc ocr0a immediate max 3 1 1 fast pwm 0xff top max table 12-2. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 12-3. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 reserved 1 0 clear oc0a on compare match. set oc0a at top 1 1 set oc0a on compare match. clear oc0a at top
111 7682c?auto?04/08 at90can32/64/128 note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 105 for more details. table 12-4 shows the com0a1:0 bit functionality when the wgm0 1:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 107 for more details. ? bit 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. if external pin modes are used for the timer/counte r0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 12.9.2 timer/counter0 register ? tcnt0 the timer/counter register gives direct access, bot h for read and write operations, to the timer/counter unit 8-bit counter. writing to the tc nt0 register blocks (removes) the compare match on the following timer clock. modifying the c ounter (tcnt0) while the counter is running, introduces a risk of missing a compare match betwee n tcnt0 and the ocr0a register. table 12-4. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 reserved 1 0 clear oc0a on compare match when up-counting. set oc0a on compare match when downcounting. 1 1 set oc0a on compare match when up-counting. clear oc0a on compare match when downcounting. table 12-5. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 0 0 1 clk i/o /(no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on fallin g edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 7 6 5 4 3 2 1 0 tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
112 7682c?auto?04/08 at90can32/64/128 12.9.3 output compare register a ? ocr0a the output compare register a contains an 8-bit val ue that is continuously compared with the counter value (tcnt0). a match can be used to gener ate an output compare interrupt, or to generate a waveform output on the oc0a pin. 12.9.4 timer/counter0 interrupt mask register ? tims k0 ? bit 7..2 ? reserved bits these are reserved bits for future use. ? bit 1 ? ocie0a: timer/counter0 output compare matc h a interrupt enable when the ocie0a bit is written to one, and the i-bi t in the status register is set (one), the timer/counter0 compare match a interrupt is enabled . the corresponding interrupt is executed if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt e nable when the toie0 bit is written to one, and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the c orresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the t ov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. 12.9.5 timer/counter0 interrupt flag register ? tifr 0 ? bit 1 ? ocf0a: output compare flag 0 a the ocf0a bit is set (one) when a compare match occ urs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. altern atively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (ti mer/counter0 compare match interrupt enable), and ocf0a are set (one), the timer/counter 0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs i n timer/counter0. tov0 is cleared by hard- ware when executing the corresponding interrupt han dling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i -bit, toie0 (timer/counter0 overflow inter- rupt enable), and tov0 are set (one), the timer/cou nter0 overflow interrupt is executed. in phase correct pwm mode, this bit is set when timer/ counter0 changes counting direction at 0x00. bit 7 6 5 4 3 2 1 0 ocr0a[7:0] ocr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ocie0a toie0 timsk0 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ocf0a tov0 tifr0 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0
113 7682c?auto?04/08 at90can32/64/128 13. 16-bit timer/counter (timer/counter1 and timer/c ounter3) the 16-bit timer/counter unit allows accurate progr am execution timing (event management), wave generation, and signal timing measurement. the main features are: 13.1 features ? true 16-bit design (i.e., allows 16-bit pwm) ? three independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (p wm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, oc f1b, and icf1 for timer/counter1 - tov3, ocf3a, ocf3b, and icf3 for timer/counter3) 13.2 overview many register and bit references in this section ar e written in general form. ? a lower case ?n? replaces the timer/counter number , in this case 1 or 3. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a, b or c. however, when using the register or bit defines in a program , the precise form must be used, i.e., ocrna for accessing timer/countern output compare c hannel a value and so on. a simplified block diagram of the 16-bit timer/coun ter is shown in figure 13-1 . for the actual placement of i/o pins, refer to ?pinout at90can32/64/128 - tqfp? on page 5 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the ?16-bit timer/counter register description? on page 135 .
114 7682c?auto?04/08 at90can32/64/128 figure 13-1. 16-bit timer/counter block diagram (1) note: 1. refer to figure 1-2 on page 5 , table 9-6 on page 76 , and table 9-15 on page 83 for timer/counter 1 and 3 pin placement and description. 13.2.1 registers the timer/counter (tcntn), output compare registers (ocrnx), and input capture register (icrn) are all 16-bit registers. special procedures must be followed when accessing the 16-bit registers. these procedures are described in the se ction ?accessing 16-bit registers? on page 116 . the timer/counter control registers (tccrnx) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbreviate d to int.req. in the figure) signals are all visibl e in the timer interrupt flag register (tifrn). all i nterrupts are individually masked with the timer interrupt mask register (timskn). tifrn and timskn are not shown in the figure. the timer/counter can be clocked internally, via th e prescaler, or by an external clock source on the tn pin. the clock select logic block controls w hich clock source and edge the timer/counter icfn (int.req.) tovn (int.req.) clock select timer/counter databus ocrna ocrnb ocrnc icrn = = = tcntn waveform generation waveform generation waveform generation ocna ocnb ocnc noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction ocfna (int.req.) ocfnb (int.req.) ocfnc (int.req.) tccrna tccrnb tccrnc ( from analog comparator ouput ) tn edge detector ( from prescaler ) clk tn
115 7682c?auto?04/08 at90can32/64/128 uses to increment (or decrement) its value. the tim er/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare registers (ocrnx ) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output co mpare pin (ocnx). see ?output compare units? on page 123. . the compare match event will also set the compare match flag (ocfnx) which can be used to generate an output compare int errupt request. the input capture register can capture the timer/co unter value at a given external (edge trig- gered) event on either the input capture pin (icpn) or on the analog comparator pins ( see ?analog comparator? on page 268. ) the input capture unit includes a digital filteri ng unit (noise canceler) for reducing the chance of capturing nois e spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocrna register, the icrn register, or by a set of fixed values. when using ocrna as top value in a pwm mode, the ocrna registe r can not be used for generating a pwm output. however, the top value will in this cas e be double buffered allowing the top value to be changed in run time. if a fixed top val ue is required, the icrn register can be used as an alternative, freeing the ocrna to be used as pwm output. 13.2.2 definitions the following definitions are used extensively thro ughout the section: 13.2.3 compatibility the 16-bit timer/counter has been updated and impro ved from previous versions of the 16-bit avr timer/counter. this 16-bit timer/counter is ful ly compatible with the earlier version regarding: ? all 16-bit timer/counter related i/o register addr ess locations, including timer interrupt registers. ? bit locations inside all 16-bit timer/counter regi sters, including timer interrupt registers. ? interrupt vectors. the following control bits have changed name, but h ave same functionality and register location: ? pwmn0 is changed to wgmn0. ? pwmn1 is changed to wgmn1. ? ctcn is changed to wgmn2. the following registers are added to the 16-bit tim er/counter: ? timer/counter control register c (tccrnc). ? output compare register c, ocrnch and ocrncl, comb ined ocrnc. bottom the counter reaches the bottom when it become s 0x0000. max the counter reaches its maximum when it becomes 0xffff (decimal 65,535). top the counter reaches the top when it becomes equal t o the highest value in the count sequence. the top value can be assigned to be one o f the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the ocr n a or icr n register. the assignment is dependent of the mode of operation.
116 7682c?auto?04/08 at90can32/64/128 the 16-bit timer/counter has improvements that will affect the compatibility in some special cases. the following bits are added to the 16-bit timer/co unter control registers: ? comnc1:0 are added to tccrna. ? focna, focnb and focnc are added to tccrnc. ? wgmn3 is added to tccrnb. interrupt flag and mask bits for output compare uni t c are added. the 16-bit timer/counter has improvements that will affect the compatibility in some special cases. 13.3 accessing 16-bit registers the tcntn, ocrnx, and icrn are 16-bit registers tha t can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byt e accessed using two read or write operations. each 16-bit timer has a single 8-bit register for t emporary storing of the high byte of the 16-bit access. the same temporary register is shared betwe en all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit r ead or write operation. when the low byte of a 16-bit register is written by the cpu, the high byt e stored in the temporary register, and the low byte written are both copied into the 16-bit regist er in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the tempo- rary register in the same clock cycle as the low by te is read. not all 16-bit accesses uses the temporary register for the high byte. reading the ocrnx 16-bit registers does not involve using the temporary regi ster. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte.
117 7682c?auto?04/08 at90can32/64/128 13.3.1 code examples the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrnx and icrn registers. note that when using ?c?, the compiler handles the 16-bit access. note: 1. the example code assumes that the part speci fic header file is included. the assembly code example returns the tcntn value i n the r17:r16 register pair. it is important to notice that accessing 16-bit reg isters are atomic operations. if an interrupt occurs between the two instructions accessing the 1 6-bit register, and the interrupt code updates the temporary register by accessing the sam e or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the tempora ry register, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff sts tcntnh,r17 sts tcntnl,r16 ; read tcntn into r17:r16 lds r16,tcntnl lds r17,tcntnh ... c code examples (1) unsigned int i; ... /* set tcntn to 0x01ff */ tcnt n = 0x1ff; /* read tcntn into i */ i = tcntn; ...
118 7682c?auto?04/08 at90can32/64/128 the following code examples show how to do an atomi c read of the tcntn register contents. reading any of the ocrnx or icrn registers can be d one by using the same principle. note: 1. the example code assumes that the part speci fic header file is included. the assembly code example returns the tcntn value i n the r17:r16 register pair. assembly code example (1) tim16_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 lds r16,tcntnl lds r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; }
119 7682c?auto?04/08 at90can32/64/128 the following code examples show how to do an atomi c write of the tcntn register contents. writing any of the ocrnx or icrn registers can be d one by using the same principle. note: 1. the example code assumes that the part speci fic header file is included. the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcntn. 13.3.2 reusing the temporary high byte register if writing to more than one 16-bit register where t he high byte is the same for all registers written, then the high byte only needs to be written once. h owever, note that the same rule of atomic operation described previously also applies in this case. 13.4 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is cont rolled by the clock select (csn2:0) bits located in the timer/counter control register b (tc crnb). for details on clock sources and prescaler, see ?timer/counter3/1/0 prescalers? on page 96 . assembly code example (1) tim16_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 sts tcntnh,r17 sts tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; }
120 7682c?auto?04/08 at90can32/64/128 13.5 counter unit the main part of the 16-bit timer/counter is the pr ogrammable 16-bit bi-directional counter unit. figure 13-2 shows a block diagram of the counter and its surro undings. figure 13-2. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. direction select between increment and decrement. clear clear tcntn (set all bits to zero). clk t n timer/counter clock. top signalize that tcntn has reached maximum value. bottom signalize that tcntn has reached minimum value (zer o). the 16-bit counter is mapped into two 8-bit i/o mem ory locations: counter high (tcntnh) con- taining the upper eight bits of the counter, and co unter low (tcntnl) containing the lower eight bits. the tcntnh register can only be indirectly ac cessed by the cpu. when the cpu does an access to the tcntnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcntnh v alue when the tcntnl is read, and tcntnh is updated with the temporary register value when tcntnl is written. this allows the cpu to read or write the entire 16-bit counter valu e within one clock cycle via the 8-bit data bus. it is important to notice that there are special ca ses of writing to the tcntn register when the counter is counting that will give unpredictable re sults. the special cases are described in the sections where they are of importance. depending on the mode of operation used, the counte r is cleared, incremented, or decremented at each timer clock (clk t n ). the clk t n can be generated from an external or internal cloc k source, selected by the clock select bits (csn2:0). when no clock source is selected (csn2:0 = 0) the timer is stopped. however, the tcntn value can be a ccessed by the cpu, independent of whether clk t n is present or not. a cpu write overrides (has prio rity over) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgmn3:0) located in the timer/counter control regi sters a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs ocnx. f or more details about advanced counting sequences and waveform generation, see ?modes of operation? on page 126 . temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector ( from prescaler ) clk tn
121 7682c?auto?04/08 at90can32/64/128 the timer/counter overflow flag (tovn) is set accor ding to the mode of operation selected by the wgmn3:0 bits. tovn can be used for generating a cpu interrupt. 13.6 input capture unit the timer/counter incorporates an input capture uni t that can capture external events and give them a time-stamp indicating time of occurrence. th e external signal indicating an event, or mul- tiple events, can be applied via the icpn pin or al ternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequency , duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be u sed for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 13-3 . the elements of the block diagram that are not directly a part of t he input capture unit are gray shaded. figure 13-3. input capture unit block diagram note: the analog comparator output (aco) can only tr igger the timer/counter1 ic unit? not timer/counter3. when a change of the logic level (an event) occurs on the input capture pin (icpn), alternatively on the analog comparator output (aco), and this cha nge confirms to the setting of the edge detector, a capture will be triggered. when a captu re is triggered, the 16-bit value of the counter (tcntn) is written to the input capture register (i crn). the input capture flag (icfn) is set at the same system clock as the tcntn value is copied into icrn register. if enabled (icien = 1), the input capture flag generates an input capture i nterrupt. the icfn flag is automatically write icrn (16-bit register) icrnh (8-bit) temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) icf1 (int.re noise canceler edge detector acic* icnc1 ices1 icp1 analog comparator aco* icf3 (int.re noise canceler icp3 edge detector icnc3 ices3
122 7682c?auto?04/08 at90can32/64/128 cleared when the interrupt is executed. alternative ly the icfn flag can be cleared by software by writing a logical one to its i/o bit location. reading the 16-bit value in the input capture regis ter (icrn) is done by first reading the low byte (icrnl) and then the high byte (icrnh). when t he low byte is read the high byte is copied into the high byte temporary register (temp). when the cpu reads the icrnh i/o location it will access the temp register. the icrn register can only be written when using a waveform generation mode that utilizes the icrn register for defining the counter?s top va lue. in these cases the waveform genera- tion mode (wgmn3:0) bits must be set before the top value can be written to the icrn register. when writing the icrn register the high b yte must be written to the icrnh i/o location before the low byte is written to icrnl. for more information on how to access the 16-bit re gisters refer to ?accessing 16-bit registers? on page 116 . 13.6.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icpn). only timer/counter1 can alternatively use the analog com parator output as trigger source for the input capture unit. the analog comparator is select ed as trigger source by setting the analog comparator input capture (acic) bit in the analog c omparator control and status register (acsr). be aware that changing trigger source can t rigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icpn) and the analog co mparator output (aco) inputs are sampled using the same technique as for the tn pin ( figure 11-1 on page 97 ). the edge detector is also identical. however, when the noise canceler is enab led, additional logic is inserted before the edge detector, which increases the delay by four sy stem clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a wave- form generation mode that uses icrn to define top. an input capture can be triggered by software by co ntrolling the port of the icpn pin. 13.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples , and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in timer/counter control register b (tccrnb). when ena bled the noise canceler introduces addi- tional four system clock cycles of delay from a cha nge applied to the input, to the update of the icrn register. the noise canceler uses the system c lock and is therefore not affected by the prescaler. 13.6.3 using the input capture unit the main challenge when using the input capture uni t is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in the icrn register be fore the next event occurs, the icrn will be overwritten with a new value. in this case the resu lt of the capture will be incorrect. when using the input capture interrupt, the icrn re gister should be read as early in the inter- rupt handler routine as possible. even though the i nput capture interrupt has relatively high
123 7682c?auto?04/08 at90can32/64/128 priority, the maximum interrupt response time is de pendent on the maximum number of clock cycles it takes to handle any of the other interrup t requests. using the input capture unit in any mode of operati on when the top value (resolution) is actively changed during operation, is not recommend ed. measurement of an external signal?s duty cycle requ ires that the trigger edge is changed after each capture. changing the edge sensing must be don e as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by software (writing a logical one to the i /o bit location). for measuring frequency only, the clearing of the icfn flag is not required (if a n interrupt handler is used). 13.7 output compare units the 16-bit comparator continuously compares tcntn w ith the output compare register (ocrnx). if tcnt equals ocrnx the comparator signal s a match. a match will set the output compare flag (ocfnx) at the next timer clock cycle. if enabled (ocienx = 1), the output com- pare flag generates an output compare interrupt. th e ocfnx flag is automatically cleared when the interrupt is executed. alternatively the o cfnx flag can be cleared by software by writ- ing a logical one to its i/o bit location. the wave form generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (comnx1:0) b its. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( see ?modes of operation? on page 126. ) a special feature of output compare unit a allows i t to define the timer/counter top value (i.e., counter resolution). in addition to the counter res olution, the top value defines the period time for waveforms generated by the waveform generator. figure 13-4 shows a block diagram of the output compare unit. the elements of the block dia- gram that are not directly a part of the output com pare unit are gray shaded.
124 7682c?auto?04/08 at90can32/64/128 figure 13-4. output compare unit, block diagram the ocrnx register is double buffered when using an y of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on comp are (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocrnx com- pare register to either top or bottom of the counti ng sequence. the synchronization prevents the occurrence of odd-length, non-symmetri cal pwm pulses, thereby making the out- put glitch-free. the ocrnx register access may seem complex, but thi s is not case. when the double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is dis- abled the cpu will access the ocrnx directly. the c ontent of the ocrnx (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icrn register). ther efore ocrnx is not read via the high byte temporary register (temp). however, it is a good pr actice to read the low byte first as when accessing other 16-bit registers. writing the ocrnx registers must be done via the temp reg- ister since the compare of all 16 bits is done cont inuously. the high byte (ocrnxh) has to be written first. when the high byte i/o location is w ritten by the cpu, the temp register will be updated by the value written. then when the low byt e (ocrnxl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx buffer or ocrnx compare register in the same system clock cycle. for more information of how to access the 16-bit re gisters refer to ?accessing 16-bit registers? on page 116 . 13.7.1 force output compare in non-pwm waveform generation modes, the match out put of the comparator can be forced by writing a one to the force output compare (focnx) b it. forcing compare match will not set the ocfnx flag or reload/clear the timer, but the ocnx pin will be updated as if a real compare ocfnx (int.req.) = (16-bit comparator ) ocrnx buffer (16-bit register) ocrnxh buf.(8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf.(8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom
125 7682c?auto?04/08 at90can32/64/128 match had occurred (the comnx1:0 bits settings defi ne whether the ocnx pin is set, cleared or toggled). 13.7.2 compare match blocking by tcntn write all cpu writes to the tcntn register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. this f eature allows ocrnx to be initialized to the same value as tcntn without triggering an interrupt when the timer/counter clock is enabled. 13.7.3 using the output compare unit since writing tcntn in any mode of operation will b lock all compare matches for one timer clock cycle, there are risks involved when changing tcntn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcntn equals the ocrnx value, the compare match wil l be missed, resulting in incorrect wave- form generation. do not write the tcntn equal to to p in pwm modes with variable top values. the compare match for the top will be ignor ed and the counter will continue to 0xffff. similarly, do not write the tcntn value equal to bo ttom when the counter is downcounting. the setup of the ocnx should be performed before se tting the data direction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output com- pare (focnx) strobe bits in normal mode. the ocnx r egister keeps its value even when changing between waveform generation modes. be aware that the comnx1:0 bits are not double buff ered together with the compare value. changing the comnx1:0 bits will take effect immedia tely. 13.8 compare match output unit the compare output mode (comnx1:0) bits have two fu nctions. the waveform generator uses the comnx1:0 bits for defining the output compare ( ocnx) state at the next compare match. secondly the comnx1:0 bits control the ocnx pin out put source. figure 13-5 shows a simplified schematic of the logic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the part s of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits ar e shown. when referring to the ocnx state, the reference is for the internal ocnx regis ter, not the ocnx pin. if a system reset occur, the ocnx register is reset to ?0?.
126 7682c?auto?04/08 at90can32/64/128 figure 13-5. compare match output unit, schematic 13.8.1 compare output function the general i/o port function is overridden by the output compare (ocnx) from the waveform generator if either of the comnx1:0 bits are set. h owever, the ocnx pin direction (input or out- put) is still controlled by the data direction regi ster (ddr) for the port pin. the data direction register bit for the ocnx pin (ddr_ocnx) must be se t as output before the ocnx value is visi- ble on the pin. the port override function is gener ally independent of the waveform generation mode, but there are some exceptions. refer to table 13-1 , table 13-2 and table 13-3 for details. the design of the output compare pin logic allows i nitialization of the ocnx state before the out- put is enabled. note that some comnx1:0 bit setting s are reserved for certain modes of operation. see ?16-bit timer/counter register description? on page 135. the comnx1:0 bits have no effect on the input captu re unit. 13.8.2 compare output mode and waveform generation the waveform generator uses the comnx1:0 bits diffe rently in normal, ctc, and pwm modes. for all modes, setting the comnx1:0 = 0 tells the w aveform generator that no action on the ocnx register is to be performed on the next compar e match. for compare output actions in the non-pwm modes refer to table 13-1 on page 136 . for fast pwm mode refer to table 13-2 on page 136 , and for phase correct and phase and frequency cor rect pwm refer to table 13-3 on page 137 . a change of the comnx1:0 bits state will have effec t at the first compare match after the bits are written. for non-pwm modes, the action can be force d to have immediate effect by using the focnx strobe bits. 13.9 modes of operation the mode of operation, i.e., the behavior of the ti mer/counter and the output compare pins, is defined by the combination of the waveform generati on mode (wgmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, port ddr d q d q ocnx pin ocnx d q waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o
127 7682c?auto?04/08 at90can32/64/128 while the waveform generation mode bits do. the com nx1:0 bits control whether the pwm out- put generated should be inverted or not (inverted o r non-inverted pwm). for non-pwm modes the comnx1:0 bits control whether the output should be set, cleared or toggle at a compare match ( see ?compare match output unit? on page 125. ) for detailed timing information refer to ?timer/counter timing diagrams? on page 134 . 13.9.1 normal mode the simplest mode of operation is the normal mode ( wgmn3:0 = 0). in this mode the counting direction is always up (incrementing), and no count er clear is performed. the counter simply overruns when it passes its maximum 16-bit value (m ax = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/coun ter overflow flag (tovn) will be set in the same timer clock cycle as the tcntn becomes zer o. the tovn flag in this case behaves like a 17th bit, except that it is only set, not cl eared. however, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by soft- ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mod e. however, observe that the maximum interval between the external events must not excee d the resolution of the counter. if the interval between events are too long, the timer overflow int errupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate in terrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 13.9.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12), the ocrna or icrn register are used to manipulate the counter resolution. in c tc mode the counter is cleared to zero when the counter value (tcntn) matches either the ocrna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12). the ocrna or icrn define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match ou tput frequency. it also simplifies the opera- tion of counting external events. the timing diagram for the ctc mode is shown in figure 13-6 . the counter value (tcntn) increases until a compare match occurs with either ocrna or icrn, and then counter (tcntn) is cleared. figure 13-6. ctc mode, timing diagram tcntn ocna (toggle) ocna interrupt flag s or icfn interrupt fla (interrupt on top) 1 4 period 2 3 (comna1:0 = 1)
128 7682c?auto?04/08 at90can32/64/128 an interrupt can be generated at each time the coun ter value reaches the top value by either using the ocfna or icfn flag according to the regis ter used to define the top value. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when th e counter is running with none or a low prescaler value must be done with care since the ct c mode does not have the double buffering feature. if the new value written to ocrna or icrn is lower than the current value of tcntn, the counter will miss the compare match. the counter wi ll then have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternative will then be to use the fast pwm mode using ocrna for defining top (wgmn3:0 = 15) since the ocr na then will be double buffered. for generating a waveform output in ctc mode, the o cna output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (comna1:0 = 1). the ocna value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_ocna = 1). the wavefo rm generated will have a maximum fre- quency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 13.9.3 fast pwm mode the fast pulse width modulation or fast pwm mode (w gmn3:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is set on the compare match between tcntn and ocrnx, and clea red at top. in inverting compare output mode output is cleared on compare match and set at top. due to the single-slope oper- ation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high fre- quency makes the fast pwm mode well suited for powe r regulation, rectification, and dac applications. high frequency allows physically smal l sized external components (coils, capaci- tors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icr n or ocrna set to 0x0003), and the max- imum resolution is 16-bit (icrn or ocrna set to max ). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until t he counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5 , 6, or 7), the value in icrn (wgmn3:0 = 14), or the value in ocrna (wgmn3:0 = 15). the coun ter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mo de is shown in figure 13-7 . the figure f ocna f clk_i/o 2 n 1 ocrna + ( ) ? ? --------------------------------------------------- = r fpwm top 1 + ( ) log 2 ( ) log ----------------------------------- =
129 7682c?auto?04/08 at90can32/64/128 shows fast pwm mode when ocrna or icrn is used to d efine top. the tcntn value is in the timing diagram shown as a histogram for illustratin g the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. figure 13-7. fast pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches top. in addition the ocna or icfn flag is set at the same timer cloc k cycle as tovn is set when either ocrna or icrn is used for defining the top value. if one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the top and c ompare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top values the unused bi ts are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updati ng ocrna when used for defining the top value. the icrn register is not double buffered. th is means that if icrn is changed to a low value when the counter is running with none or a lo w prescaler value, there is a risk that the new icrn value written is lower than the current value of tcntn. the result will then be that the counter will miss the compare match at the top valu e. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x00 00 before the compare match can occur. the ocrna register however, is double buffered. thi s feature allows the ocrna i/o location to be written anytime. when the ocrna i/o location is written the value written will be put into the ocrna buffer register. the ocrna compare regist er will then be updated with the value in the buffer register at the next timer clock cycl e the tcntn matches top. the update is done at the same timer clock cycle as the tcntn is clear ed and the tovn flag is set. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for gen erating a pwm output on ocna. however, if the base pwm frequency is actively changed (by c hanging the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. tcntn ocrnx/top update and tovn interrupt flag set ocna interrupt flag set or icfn interrupt flag s (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3)
130 7682c?auto?04/08 at90can32/64/128 in fast pwm mode, the compare units allow generatio n of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non -inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three ( see table on page 136 ). the actual ocnx value will only be visible on the port pin if the d ata direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by settin g (or clearing) the ocnx register at the compare match between ocrnx and tcntn, and clea ring (or setting) the ocnx register at the timer clock cycle the counter is cleared (chang es from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent s special cases when generating a pwm waveform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) the out- put will be a narrow spike for each top+1 timer clo ck cycle. setting the ocrnx equal to top will result in a constant high or low output (depen ding on the polarity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) waveform output i n fast pwm mode can be achieved by set- ting ocna to toggle its logical level on each compa re match (comna1:0 = 1). the waveform generated will have a maximum frequency of f oc n a = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna toggl e in ctc mode, except the double buffer fea- ture of the output compare unit is enabled in the f ast pwm mode. 13.9.4 phase correct pwm mode the phase correct pulse width modulation or phase c orrect pwm mode (wgmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequ ency correct pwm mode, based on a dual- slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode , the output compare (ocnx) is cleared on the compare match between tcntn and ocrn x while upcounting, and set on the compare match while downcounting. in inverting outp ut compare mode, the operation is inverted. the dual-slope operation has lower maximu m operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode c an be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution all owed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolu- tion in bits can be calculated by using the followi ng equation: in phase correct pwm mode the counter is incremente d until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff ( wgmn3:0 = 1, 2, or 3), the value in icrn (wgmn3:0 = 10), or the value in ocrna (wgmn3:0 = 11 ). the counter has then reached the top and changes the count direction. the tcntn valu e will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 13-8 . the figure shows phase correct pwm mode when ocrna or icrn is used to define top. the tcntn f ocnxpwm f clk_i/o n 1 top + ( ) ? ----------------------------------- = r pcpwm top 1 + ( ) log 2 ( ) log ----------------------------------- =
131 7682c?auto?04/08 at90can32/64/128 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outp uts. the small horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx inter- rupt flag will be set when a compare match occurs. figure 13-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the counter reaches bottom. when either ocrna or icrn is used for defining the top v alue, the ocna or icfn flag is set accord- ingly at the same timer clock cycle as the ocrnx re gisters are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top values, the unused b its are masked to zero when any of the ocrnx registers are written. as the third period sh own in figure 13-8 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be fo und in the time of update of the ocrnx reg- ister. since the ocrnx update occurs at top, the pw m period starts and ends at top. this implies that the length of the falling slope is det ermined by the previous top value, while the length of the rising slope is determined by the new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency co rrect mode instead of the phase correct mode when changing the top value while the timer/co unter is running. when using a static top value there are practically no differences betw een the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will pr oduce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 137 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set a s ocrnx/top update and ocna interrupt flag se or icfn interrupt flag (interrupt on top) 1 2 3 4 tovn interrupt flag se (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2 (comnx1:0 = 3
132 7682c?auto?04/08 at90can32/64/128 output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx regis- ter at the compare match between ocrnx and tcntn wh en the counter increments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pwm frequency for the o utput when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if t he ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. 13.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulat ion, or phase and frequency correct pwm mode (wgmn3:0 = 8 or 9) provides a high resolution phase and frequency correct pwm wave- form generation option. the phase and frequency cor rect pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the coun ter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non -inverting compare output mode, the output compare (ocnx) is cleared on the compare mat ch between tcntn and ocrnx while upcounting, and set on the compare match while down counting. in inverting compare output mode, the operation is inverted. the dual-slope ope ration gives a lower maximum operation fre- quency compared to the single-slope operation. howe ver, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocrnx register is updated by t he ocrnx buffer register, (see figure 13- 8 and figure 13-9 ). the pwm resolution for the phase and frequency corr ect pwm mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2- bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icrn (wgmn3:0 = 8), or the value in ocrna (wgmn3:0 = 9). the counter has then reached the top and changes the co unt direction. the tcntn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 13-9 . the figure shows phase and frequency correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing dia- gram shown as a histogram for illustrating the dual -slope operation. the diagram includes non- inverted and inverted pwm outputs. the small horizo ntal line marks on the tcntn slopes repre- sent compare matches between ocrnx and tcntn. the o cnx interrupt flag will be set when a compare match occurs. f ocnxpcpwm f clk_i/o 2 n top ? ? ---------------------------- = r pfcpwm top 1 + ( ) log 2 ( ) log ----------------------------------- =
133 7682c?auto?04/08 at90can32/64/128 figure 13-9. phase and frequency correct pwm mode, timing diagra m the timer/counter overflow flag (tovn) is set at th e same timer clock cycle as the ocrnx registers are updated with the double buffer value (at bottom). when either ocrna or icrn is used for defining the top value, the ocna or icf n flag set when tcntn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. as figure 13-9 shows the output generated is, in contrast to the phase correct mode, symmetri- cal in all periods. since the ocrnx registers are u pdated at bottom, the length of the rising and the falling slopes will always be equal. this g ives symmetrical output pulses and is therefore frequency correct. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for gen erating a pwm output on ocna. however, if the base pwm frequency is actively changed by ch anging the top value, using the ocrna as top is clearly a better choice due to its double bu ffer feature. in phase and frequency correct pwm mode, the compar e units allow generation of pwm wave- forms on the ocnx pins. setting the comnx1:0 bits t o two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 137 ). the actual ocnx value will only be visible on th e port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm wavef orm is generated by setting (or clearing) the ocnx register at the compare match between ocrn x and tcntn when the counter incre- ments, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pwm frequenc y for the output when using phase and frequency correct pwm can be calculated by the following equation: ocrnx/top update and tovn interrupt flag se (interrupt on bottom) ocna interrupt flag se or icfn interrupt flag (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2 n top ? ? ???????????????????????????? =
134 7682c?auto?04/08 at90can32/64/128 the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represent s special cases when generating a pwm waveform output in the phase correct pwm mode. if t he ocrnx is set equal to bottom the output will be continuously low and if set equal to top the output will be set to high for non- inverted pwm mode. for inverted pwm the output will have the opposite logic values. 13.10 timer/counter timing diagrams the timer/counter is a synchronous design and the t imer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the f igures include information on when interrupt flags are set, and when the ocrnx register is updat ed with the ocrnx buffer value (only for modes utilizing double buffering). figure 13-10 shows a timing diagram for the setting of ocfnx. figure 13-10. timer/counter timing diagram, setting of ocfnx, no prescaling figure 13-11 shows the same timing data, but with the prescaler enabled. figure 13-11. timer/counter timing diagram, setting of ocfnx, wit h prescaler (f clk_i/o /8) figure 13-12 shows the count sequence close to top in various m odes. when using phase and frequency correct pwm mode the ocrnx register is up dated at bottom. the timing diagrams will be the same, but top should be replaced by bot tom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the to vn flag at bottom. clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8)
135 7682c?auto?04/08 at90can32/64/128 figure 13-12. timer/counter timing diagram, no prescaling figure 13-13 shows the same timing data, but with the prescaler enabled. figure 13-13. timer/counter timing diagram, with prescaler (f clk_i/o /8) 13.11 16-bit timer/counter register description 13.11.1 timer/counter1 control register a ? tccr1a 13.11.2 timer/counter3 control register a ? tccr3a tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icfn (ifused as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 tccr1 a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 tccr3 a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
136 7682c?auto?04/08 at90can32/64/128 ? bit 7:6 ? comna1:0: compare output mode for channe l a ? bit 5:4 ? comnb1:0: compare output mode for channe l b ? bit 3:2 ? comnc1:0: compare output mode for channe l c the comna1:0, comnb1:0 and comnc1:0 control the out put compare pins (ocna, ocnb and ocnc respectively) behavior. if one or both of the comna1:0 bits are written to one, the ocna output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bit are written to one, the oc nb output overrides the normal port func- tionality of the i/o pin it is connected to. if one or both of the comnc1:0 bit are written to one, the ocnc output overrides the normal port functiona lity of the i/o pin it is connected to. how- ever, note that the data direction register (ddr) b it corresponding to the ocna, ocnb or ocnc pin must be set in order to enable the output driver. when the ocna, ocnb or ocnc is connected to the pin , the function of the comnx1:0 bits is dependent of the wgmn3:0 bits setting. table 13-1 shows the comnx1:0 bit functionality when the wgmn3:0 bits are set to a normal or a ctc mode (non-pwm). table 13-2 shows the comnx1:0 bit functionality when the wgmn 3:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocrna/ocrnb/ocrnc equals top and comna1/comnb1/comnc1 is set. in this case the compa re match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 128. for more details. table 13-1. compare output mode, non-pwm comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 0 0 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 toggle ocna/ocnb/ocnc on compare match. 1 0 clear ocna/ocnb/ocnc on compare match (set output to low level). 1 1 set ocna/ocnb/ocnc on compare match (set output to high level). table 13-2. compare output mode, fast pwm (1) comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 0 0 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 wgmn3=0: normal port operation, ocna/ocnb/ocnc disconnected. wgmn3=1: toggle ocna on compare match, ocnb/ocnc reserved. 1 0 clear ocna/ocnb/ocnc on compare match set ocna/ocnb/ocnc at top 1 1 set ocna/ocnb/ocnc on compare match clear ocna/ocnb/ocnc at top
137 7682c?auto?04/08 at90can32/64/128 table 13-3 shows the comnx1:0 bit functionality when the wgmn 3:0 bits are set to the phase correct or the phase and frequency correct, pwm mod e. note: 1. a special case occurs when ocna/ocnb/ocnc eq uals top and comna1/comnb1/comnc1 is set. see ?phase correct pwm mode? on page 130. for more details. ? bit 1:0 ? wgmn1:0: waveform generation mode combined with the wgmn3:2 bits found in the tccrnb register, these bits control the counting sequence of the counter, the source for maximum (to p) counter value, and what type of wave- form generation to be used, see table 13-4 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on com pare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( see ?modes of operation? on page 126. ). table 13-3. compare output mode, phase correct and phase and fr equency correct pwm (1) comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 0 0 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 wgmn3=0: normal port operation, ocna/ocnb/ocnc disconnected. wgmn3=1: toggle ocna on compare match, ocnb/ocnc reserved. 1 0 clear ocna/ocnb/ocnc on compare match when up-counting. set ocna/ocnb/ocnc on compare match when downcounting. 1 1 set ocna/ocnb/ocnc on compare match when up- counting. clear ocna/ocnb/ocnc on compare match when downcounting.
138 7682c?auto?04/08 at90can32/64/128 note: 1. the ctcn and pwmn1:0 bit definition names ar e obsolete. use the wgm n2:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 13.11.3 timer/counter1 control register b ? tccr1b 13.11.4 timer/counter3 control register b ? tccr3b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input captu re noise canceler. when the noise canceler is activated, the input from the input capture pin (ic pn) is filtered. the filter function requires four successive equal valued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles when th e noise canceler is enabled. ? bit 6 ? icesn: input capture edge select table 13-4. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrnx at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10- bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 8 1 0 0 0 pwm, phase and frequency correct icrn bottom bottom 9 1 0 0 1 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icrn top top 15 1 1 1 1 fast pwm ocrna top top bit 7 6 5 4 3 2 1 0 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 tccr3b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
139 7682c?auto?04/08 at90can32/64/128 this bit selects which edge on the input capture pi n (icpn) that is used to trigger a capture event. when the icesn bit is written to zero, a fal ling (negative) edge is used as trigger, and when the icesn bit is written to one, a rising (pos itive) edge will trigger the capture. when a capture is triggered according to the icesn setting, the counter value is copied into the input capture register (icrn). the event will also set the input capture flag (icfn), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icrn is used as top value (see description of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is discon nected and consequently the input cap- ture function is disabled. ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring c ompatibility with future devices, this bit must be written to zero when tccrnb is written. ? bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. ? bit 2:0 ? csn2:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 13-10 and figure 13-11 . if external pin modes are used for the timer/counte rn, transitions on the tn pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 13.11.5 timer/counter1 control register c ? tccr1c table 13-5. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped). 0 0 1 clk i/o /1 (no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on fallin g edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7 6 5 4 3 2 1 0 foc1a foc1b foc1c ? ? ? ? ? tccr1c read/write r/w r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0
140 7682c?auto?04/08 at90can32/64/128 13.11.6 timer/counter3 control register c ? tccr3c ? bit 7 ? focna: force output compare for channel a ? bit 6 ? focnb: force output compare for channel b ? bit 5 ? focnc: force output compare for channel c the focna/focnb/focnc bits are only active when the wgmn3:0 bits specifies a non-pwm mode. however, for ensuring compatibility with futu re devices, these bits must be set to zero when tccrna is written when operating in a pwm mode . when writing a logical one to the focna/focnb/focnc bit, an immediate compare match i s forced on the waveform genera- tion unit. the ocna/ocnb/ocnc output is changed acc ording to its comnx1:0 bits setting. note that the focna/focnb/focnc bits are implemente d as strobes. therefore it is the value present in the comnx1:0 bits that determine the eff ect of the forced compare. a focna/focnb/focnc strobe will not generate any in terrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocrna as to p. the focna/focnb/focnc bits are always read as zero. 13.11.7 timer/counter1 ? tcnt1h and tcnt1l 13.11.8 timer/counter3 ? tcnt3h and tcnt3l the two timer/counter i/o locations (tcntnh and tcn tnl, combined tcntn) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read an d written simultaneously when the cpu accesses these registers, the access is performed u sing an 8-bit temporary high byte register (temp). this temporary register is shared by all th e other 16-bit registers. see ?accessing 16-bit registers? on page 116. modifying the counter (tcntn) while the counter is running introduces a risk of missing a com- pare match between tcntn and one of the ocrnx regis ters. writing to the tcntn register blocks (removes) the compare match on the following timer clock for all compare units. bit 7 6 5 4 3 2 1 0 foc3a foc3b foc3c ? ? ? ? ? tccr3c read/write r/w r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 tcnt3[15:8] tcnt3h tcnt3[7:0] tcnt3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
141 7682c?auto?04/08 at90can32/64/128 13.11.9 output compare register a ? ocr1ah and ocr1a l 13.11.10 output compare register b ? ocr1bh and ocr1 bl 13.11.11 output compare register c ? ocr1ch and ocr1 cl 13.11.12 output compare register a ? ocr3ah and ocr3 al 13.11.13 output compare register b ? ocr3bh and ocr3 bl 13.11.14 output compare register c ? ocr3ch and ocr3 cl the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcntn). a match can be used to gener ate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this tem porary register is shared by all the other 16- bit registers. see ?accessing 16-bit registers? on page 116. bit 7 6 5 4 3 2 1 0 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ocr1c[15:8] ocr1ch ocr1c[7:0] ocr1cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ocr3a[15:8] ocr3ah ocr3a[7:0] ocr3al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ocr3b[15:8] ocr3bh ocr3b[7:0] ocr3bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ocr3c[15:8] ocr3ch ocr3c[7:0] ocr3cl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
142 7682c?auto?04/08 at90can32/64/128 13.11.15 input capture register ? icr1h and icr1l 13.11.16 input capture register ? icr3h and icr3l the input capture is updated with the counter (tcnt n) value each time an event occurs on the icpn pin (or optionally on the analog comparator ou tput for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to en sure that both the high and low bytes are read simultaneously when the cpu accesses these register s, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 116. 13.11.17 timer/counter1 interrupt mask register ? ti msk1 13.11.18 timer/counter3 interrupt mask register ? ti msk3 ? bit 7..6 ? reserved bits these bits are reserved for future use. ? bit 5 ? icien: input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern input capture interrup t is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the icfn flag, located in tifrn, is set. ? bit 4 ? reserved bit this bit is reserved for future use. ? bit 3 ? ocienc: output compare c match interrupt e nable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare c match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the ocfnc flag, located in tifrn, is set. bit 7 6 5 4 3 2 1 0 icr1[15:8] icr1h icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 icr3[15:8] icr3h icr3[7:0] icr3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? icie1 ? ocie1c ocie1b ocie1a toie1 timsk1 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? icie3 ? ocie3c ocie3b ocie3a toie3 timsk3 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
143 7682c?auto?04/08 at90can32/64/128 ? bit 2 ? ocienb: output compare b match interrupt e nable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare b match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the ocfnb flag, located in tifrn, is set. ? bit 1 ? ociena: output compare a match interrupt e nable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare a match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the ocfna flag, located in tifrn, is set. ? bit 0 ? toien: timer/counter overflow interrupt en able when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern overflow interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 60. ) is executed when the tovn flag, located in tifrn, is set. 13.11.19 timer/counter1 interrupt flag register ? ti fr1 13.11.20 timer/counter3 interrupt flag register ? ti fr3 ? bit 7..6 ? reserved bits these bits are reserved for future use. ? bit 5 ? icfn: input capture flag this flag is set when a capture event occurs on the icpn pin. when the input capture register (icrn) is set by the wgmn3:0 to be used as the top value, the icfn flag is set when the counter reaches the top value. icfn is automatically cleared when the input captur e interrupt vector is executed. alternatively, icfn can be cleared by writing a logic one to its b it location. ? bit 4 ? reserved bit this bit is reserved for future use. ? bit 3 ? ocfnc: output compare c match flag this flag is set in the timer clock cycle after the counter (tcntn) value matches the output compare register c (ocrnc). note that a forced output compare (focnc) strobe wi ll not set the ocfnc flag. ocfnc is automatically cleared when the output comp are match c interrupt vector is exe- cuted. alternatively, ocfnc can be cleared by writi ng a logic one to its bit location. bit 7 6 5 4 3 2 1 0 ? ? icf1 ? ocf1c ocf1b ocf1a tov1 tifr1 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? icf3 ? ocf3c ocf3b ocf3a tov3 tifr3 read/write r r r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
144 7682c?auto?04/08 at90can32/64/128 ? bit 2 ? ocfnb: output compare b match flag this flag is set in the timer clock cycle after the counter (tcntn) value matches the output compare register b (ocrnb). note that a forced output compare (focnb) strobe wi ll not set the ocfnb flag. ocfnb is automatically cleared when the output comp are match b interrupt vector is exe- cuted. alternatively, ocfnb can be cleared by writi ng a logic one to its bit location. ? bit 1 ? ocfna: output compare a match flag this flag is set in the timer clock cycle after the counter (tcntn) value matches the output compare register a (ocrna). note that a forced output compare (focna) strobe wi ll not set the ocfna flag. ocfna is automatically cleared when the output comp are match a interrupt vector is exe- cuted. alternatively, ocfna can be cleared by writi ng a logic one to its bit location. ? bit 0 ? tovn: timer/counter overflow flag the setting of this flag is dependent of the wgmn3: 0 bits setting. in normal and ctc modes, the tovn flag is set when the timer overflows. refe r to table 13-4 on page 138 for the tovn flag behavior when using another wgmn3:0 bit settin g. tovn is automatically cleared when the timer/counte rn overflow interrupt vector is executed. alternatively, tovn can be cleared by writing a log ic one to its bit location.
145 7682c?auto?04/08 at90can32/64/128 14. 8-bit timer/counter2 with pwm and asynchronous o peration timer/counter2 is a general purpose, single channel , 8-bit timer/counter module. the main features are: 14.1 features ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (p wm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare match interrupt sources (tov2 and ocf2a) ? allows clocking from external 32 khz watch crystal independent of the i/o clock 14.2 overview many register and bit references in this section ar e written in general form. ? a lower case ?n? replaces the timer/counter number , in this case 2. however, when using the register or bit defines in a program, the preci se form must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a. however, when using the register or bit defines in a program, the precise form must be used, i.e., ocr2a for accessing timer/counter2 output compare channel a v alue and so on. a simplified block diagram of the 8-bit timer/count er is shown in figure 14-1 . for the actual placement of i/o pins, refer to figure 1-2 on page 5 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-sp ecific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 156 .
146 7682c?auto?04/08 at90can32/64/128 figure 14-1. 8-bit timer/counter2 block diagram the timer/counter (tcnt2) and output compare regist er (ocr2a) are 8-bit registers. inter- rupt request (shorten as int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are individually masked wit h the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, via th e prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section . the asynchronous operation is controlled by the asynchronous status register (assr). the clock select logic block controls which clock source the timer/counter uses to increment (or decr ement) its value. the timer/counter is inac- tive when no clock source is selected. the output f rom the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a) is compared with the timer/counter value at all times. the result of the compare can b e used by the waveform generator to gener- ate a pwm or variable frequency output on the outpu t compare pin (oc2a). see ?output compare unit? on page 148. for details. the compare match event will also set the compare flag (ocf2a) which can be used to generate an output com pare interrupt request. timer/counter data bus = tcntn waveform generation ocnx = 0 control logic = 0xff top bottom count clear direction tovn (int.req.) ocnx (int.req.) synchronization unit ocrnx tccrnx assrn status flags clk i/o clk asy synchronized status flags asynchronous mode select (asn) tosc2 t/c oscillator tosc1 prescaler clk tn clk i/o
147 7682c?auto?04/08 at90can32/64/128 14.2.1 definitions the following definitions are used extensively thro ughout the section: 14.3 timer/counter clock sources the timer/counter can be clocked by an internal syn chronous or an external asynchronous clock source. the clock source is selected by the c lock select logic which is controlled by the clock select (cs22:0) bits located in the timer/cou nter control register (tccr2).the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the clock source is taken from the timer/counter oscillator connected to tosc1 and tosc2 or directly from tosc1. for details on asynchronous operation, see ?asyn- chronous status register ? assr? on page 159 . for details on clock sources and prescaler, see ?timer/counter2 prescaler? on page 162 . 14.4 counter unit the main part of the 8-bit timer/counter is the pro grammable bi-directional counter unit. figure 14-2 shows a block diagram of the counter and its surro unding environment. figure 14-2. counter unit block diagram figure 14-3. signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk t 2 timer/counter clock. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (ze ro). bottom the counter reaches the bottom when it become s zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equa l to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. th e assignment is depen- dent on the mode of operation. data bus tcntn control logic count tovn (int.req.) top bottom direction clear tosc2 t/c oscillator tosc1 prescaler clk i/o clk tn clk tns
148 7682c?auto?04/08 at90can32/64/128 depending on the mode of operation used, the counte r is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal cloc k source, selected by the clock select bits (cs22:0). when no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tcnt2 value can be a ccessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has prio rity over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a). there are close connections between how the counter behaves (counts) and how waveforms are gene rated on the output compare output oc2a. for more details about advanced counting sequ ences and waveform generation, see ?modes of operation? on page 150 . the timer/counter overflow flag (tov2) is set accor ding to the mode of operation selected by the wgm21:0 bits. tov2 can be used for generating a cpu interrupt. 14.5 output compare unit the 8-bit comparator continuously compares tcnt2 wi th the output compare register (ocr2a). whenever tcnt2 equals ocr2a, the comparato r signals a match. a match will set the output compare flag (ocf2a) at the next timer c lock cycle. if enabled (ocie2a = 1), the output compare flag generates an output compare int errupt. the ocf2a flag is automatically cleared when the interrupt is executed. alternative ly, the ocf2a flag can be cleared by software by writing a logical one to its i/o bit location. t he waveform generator uses the match signal to generate an output according to operating mode set by the wgm21:0 bits and compare output mode (com2a1:0) bits. the max and bottom signals ar e used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( ?modes of oper- ation? on page 150 ). figure 14-4 shows a block diagram of the output compare unit. figure 14-4. output compare unit, block diagram the ocr2a register is double buffered when using an y of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (c tc) modes of operation, the double buffering is disabled. the double buffering synchro nizes the update of the ocr2a compare ocfn x (int.req. = (8-bit comparator ) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom
149 7682c?auto?04/08 at90can32/64/128 register to either top or bottom of the counting se quence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulse s, thereby making the output glitch-free. the ocr2a register access may seem complex, but thi s is not case. when the double buffer- ing is enabled, the cpu has access to the ocr2a buf fer register, and if double buffering is disabled the cpu will access the ocr2a directly. 14.5.1 force output compare in non-pwm waveform generation modes, the match out put of the comparator can be forced by writing a one to the force output compare (foc2a) b it. forcing compare match will not set the ocf2a flag or reload/clear the timer, but the oc2a pin will be updated as if a real compare match had occurred (the com2a1:0 bits settings defi ne whether the oc2a pin is set, cleared or toggled). 14.5.2 compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any compare match that occurs in the next timer clock cycle, even when the timer is stop ped. this feature allows ocr2a to be initial- ized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. 14.5.3 using the output compare unit since writing tcnt2 in any mode of operation will b lock all compare matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compare channel, independently of whether the timer/counter is runni ng or not. if the value written to tcnt2 equals the ocr2a value, the compare match will be m issed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is downcounting. the setup of the oc2a should be performed before se tting the data direction register for the port pin to output. the easiest way of setting the oc2a value is to use the force output com- pare (foc2a) strobe bit in normal mode. the oc2a re gister keeps its value even when changing between waveform generation modes. be aware that the com2a1:0 bits are not double buff ered together with the compare value. changing the com2a1:0 bits will take effect immedia tely. 14.6 compare match output unit the compare output mode (com2a1:0) bits have two fu nctions. the waveform generator uses the com2a1:0 bits for defining the output comp are (oc2a) state at the next compare match. also, the com2a1:0 bits control the oc2a pin output source. figure 14-5 shows a sim- plified schematic of the logic affected by the com2 a1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control regis- ters (ddr and port) that are affected by the com2a1 :0 bits are shown. when referring to the oc2a state, the reference is for the internal oc2a register, not the oc2a pin.
150 7682c?auto?04/08 at90can32/64/128 figure 14-5. compare match output unit, schematic 14.6.1 compare output function the general i/o port function is overridden by the output compare (oc2a) from the waveform generator if either of the com2a1:0 bits are set. h owever, the oc2a pin direction (input or out- put) is still controlled by the data direction regi ster (ddr) for the port pin. the data direction register bit for the oc2a pin (ddr_oc2a) must be se t as output before the oc2a value is vis- ible on the pin. the port override function is inde pendent of the waveform generation mode. the design of the output compare pin logic allows i nitialization of the oc2a state before the output is enabled. note that some com2a1:0 bit sett ings are reserved for certain modes of operation. see ?8-bit timer/counter register description? on p age 156. 14.6.2 compare output mode and waveform generation the waveform generator uses the com2a1:0 bits diffe rently in normal, ctc, and pwm modes. for all modes, setting the com2a1:0 = 0 tells the w aveform generator that no action on the oc2a register is to be performed on the next compar e match. for compare output actions in the non-pwm modes refer to table 14-2 on page 157 . for fast pwm mode, refer to table 14-3 on page 157 , and for phase correct pwm refer to table 14-4 on page 158 . a change of the com2a1:0 bits state will have effec t at the first compare match after the bits are written. for non-pwm modes, the action can be force d to have immediate effect by using the foc2a strobe bits. 14.7 modes of operation the mode of operation, i.e., the behavior of the ti mer/counter and the output compare pins, is defined by the combination of the waveform generati on mode (wgm21:0) and compare output mode (com2a1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com 2a1:0 bits control whether the pwm output generated should be inverted or not (inverte d or non-inverted pwm). for non-pwm modes the com2a1:0 bits control whether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 149. ). port ddr d q d q ocnx pin ocnx d q waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o
151 7682c?auto?04/08 at90can32/64/128 for detailed timing information refer to ?timer/counter timing diagrams? on page 154 . 14.7.1 normal mode the simplest mode of operation is the normal mode ( wgm21:0 = 0). in this mode the counting direction is always up (incrementing), and no count er clear is performed. the counter simply overruns when it passes its maximum 8-bit value (to p = 0xff) and then restarts from the bot- tom (0x00). in normal operation the timer/counter o verflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero. the to v2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. howev er, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode , a new counter value can be written anytime. the output compare unit can be used to generate int errupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 14.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm21:0 = 2) , the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater contr ol of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 14-6 . the counter value (tcnt2) increases until a compare match occurs between tcnt 2 and ocr2a, and then counter (tcnt2) is cleared. figure 14-6. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interr upt handler routine can be used for updating the top value. however, changing the top to a value clo se to bottom when the counter is run- ning with none or a low prescaler value must be don e with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compare m atch. the counter will then have to count to its maximum value (0xff) and wrap around starting a t 0x00 before the compare match can occur. tcntn ocnx (toggle) ocnx interrupt flag s 1 4 period 2 3 (comnx1:0 = 1)
152 7682c?auto?04/08 at90can32/64/128 for generating a waveform output in ctc mode, the o c2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform generated wi ll have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform f requency is defined by the following equation: the n variable represents the prescale factor (1, 8 , 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 14.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (w gm21:0 = 3) provides a high frequency pwm waveform generation option. the fast pwm differ s from the other pwm option by its sin- gle-slope operation. the counter counts from bottom to max then restarts from bottom. in non-inverting compare output mode, the output compa re (oc2a) is cleared on the compare match between tcnt2 and ocr2a, and set at bottom. i n inverting compare output mode, the output is set on compare match and cleared at b ottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that uses dual-slope operation. this high freq uency makes the fast pwm mode well suited for power regulation, rectification, and dac applic ations. high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the max value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 14-7 . the tcnt2 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line mar ks on the tcnt2 slopes represent compare matches between ocr2a and tcnt2. figure 14-7. fast pwm mode, timing diagram f ocnx f clk_i/o 2 n 1 ocrnx + ( ) ? ? -------------------------------------------------- = tcntn ocrnx update and tovn interrupt flag s 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag 4 5 6 7
153 7682c?auto?04/08 at90can32/64/128 the timer/counter overflow flag (tov2) is set each time the counter reaches max. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generatio n of pwm waveforms on the oc2a pin. setting the com2a1:0 bits to two will produce a non -inverted pwm and an inverted pwm output can be generated by setting the com2a1:0 to three ( see table 14-3 on page 157 ). the actual oc2a value will only be visible on the port pin if the data direction for the port pin is set as out- put. the pwm waveform is generated by setting (or c learing) the oc2a register at the compare match between ocr2a and tcnt2, and clearing (or set ting) the oc2a register at the timer clock cycle the counter is cleared (changes from ma x to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8 , 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr2a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on th e polarity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output i n fast pwm mode can be achieved by set- ting oc2a to toggle its logical level on each compa re match (com2a1:0 = 1). the waveform generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero. this feature is similar to the oc2a toggle in ctc mode, except the double buffer feature of the out- put compare unit is enabled in the fast pwm mode. 14.7.4 phase correct pwm mode the phase correct pwm mode (wgm21:0 = 1) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm m ode is based on a dual-slope operation. the counter counts repeatedly from bottom to max an d then from max to bottom. in non- inverting compare output mode, the output compare ( oc2a) is cleared on the compare match between tcnt2 and ocr2a while upcounting, and set o n the compare match while down- counting. in inverting output compare mode, the ope ration is inverted. the dual-slope operation has lower maximum operation frequency than single s lope operation. however, due to the sym- metric feature of the dual-slope pwm modes, these m odes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode i s fixed to eight bits. in phase correct pwm mode the counter is incremented until the count er value matches max. when the counter reaches max, it changes the count direction. the tc nt2 value will be equal to max for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 14-8 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and in verted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare ma tches between ocr2a and tcnt2. f ocnxpwm f clk_i/o n 256 ? ------------------ =
154 7682c?auto?04/08 at90can32/64/128 figure 14-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2a pin. setting the com2a1:0 bits to two will pro duce a non-inverted pwm. an inverted pwm output can be generated by setting the com2a1:0 to three (see table 14-4 on page 158 ). the actual oc2a value will only be visible on the p ort pin if the data direction for the port pin is set as output. the pwm waveform is generated by cle aring (or setting) the oc2a register at the compare match between ocr2a and tcnt2 when the coun ter increments, and setting (or clearing) the oc2a register at compare match betwee n ocr2a and tcnt2 when the counter decrements. the pwm frequency for the output when u sing phase correct pwm can be calcu- lated by the following equation: the n variable represents the prescale factor (1, 8 , 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if t he ocr2a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for non-inverted pwm mode. for inverted pwm the output will have the opposite logic values. 14.8 timer/counter timing diagrams the following figures show the timer/counter in syn chronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asy nchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures inc lude information on when interrupt flags are set. figure 14-9 contains timing data for basic timer/counter opera tion. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. tovn interrupt flag s ocnx interrupt flag s 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? ?????????????????? =
155 7682c?auto?04/08 at90can32/64/128 figure 14-9. timer/counter timing diagram, no prescaling figure 14-10 shows the same timing data, but with the prescaler enabled. figure 14-10. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 14-11 shows the setting of ocf2a in all modes except ctc mode. figure 14-11. timer/counter timing diagram, setting of ocf2a, wit h prescaler (f clk_i/o /8) clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8)
156 7682c?auto?04/08 at90can32/64/128 figure 14-12 shows the setting of ocf2a and the clearing of tcn t2 in ctc mode. figure 14-12. timer/counter timing diagram, clear timer on compar e match mode, with pres- caler (f clk_i/o /8) 14.9 8-bit timer/counter register description 14.9.1 timer/counter2 control register a? tccr2a ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bits spec ify a non-pwm mode. however, for ensur- ing compatibility with future devices, this bit mus t be set to zero when tccr2a is written when operating in pwm mode. when writing a logical one t o the foc2a bit, an immediate compare match is forced on the waveform generation unit. th e oc2a output is changed according to its com2a1:0 bits setting. note that the foc2a bit is i mplemented as a strobe. therefore it is the value present in the com2a1:0 bits that determines the effect of the forced compare. a foc2a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6, 3 ? wgm21:0: waveform generation mode these bits control the counting sequence of the cou nter, the source for the maximum (top) counter value, and what type of waveform generation to be used. modes of operation supported by the timer/counter unit are: normal mode, clear t imer on compare match (ctc) mode, and ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 7 6 5 4 3 2 1 0 foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 tccr2a read/write w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
157 7682c?auto?04/08 at90can32/64/128 two types of pulse width modulation (pwm) modes. se e table 14-1 and ?modes of operation? on page 150 . note: 1. the ctc2 and pwm2 bit definition names are n ow obsolete. use the wgm21:0 definitions. however, the functionality and location of these bi ts are compatible with previous versions of the timer. ? bit 5:4 ? com2a1:0: compare match output mode a these bits control the output compare pin (oc2a) be havior. if one or both of the com2a1:0 bits are set, the oc2a output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm21:0 bit setting. table 14-2 shows the com2a1:0 bit functionality when the wgm2 1:0 bits are set to a normal or ctc mode (non-pwm). table 14-3 shows the com2a1:0 bit functionality when the wgm2 1:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 152 for more details. table 14-1. waveform generation mode bit description (1) mode wgm21 (ctc2) wgm20 (pwm2) timer/counter mode of operation top update of ocr2a at tov2 flag set on 0 0 0 normal 0xff immediate max 1 0 1 pwm, phase correct 0xff top bottom 2 1 0 ctc ocr2a immediate max 3 1 1 fast pwm 0xff top max table 14-2. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 toggle oc2a on compare match. 1 0 clear oc2a on compare match. 1 1 set oc2a on compare match. table 14-3. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 reserved 1 0 clear oc2a on compare match. set oc2a at top. 1 1 set oc2a on compare match. clear oc2a at top.
158 7682c?auto?04/08 at90can32/64/128 table 14-4 shows the com21:0 bit functionality when the wgm21 :0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 153 for more details. ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 14-5 . 14.9.2 timer/counter2 register ? tcnt2 the timer/counter register gives direct access, bot h for read and write operations, to the timer/counter unit 8-bit counter. writing to the tc nt2 register blocks (removes) the compare match on the following timer clock. modifying the c ounter (tcnt2) while the counter is running, introduces a risk of missing a compare match betwee n tcnt2 and the ocr2a register. 14.9.3 output compare register a ? ocr2a table 14-4. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 reserved 1 0 clear oc2a on compare match when up-counting. set oc2a on compare match when downcounting. 1 1 set oc2a on compare match when up-counting. clear oc2a on compare match when downcounting. table 14-5. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 0 0 1 clk t2s /(no prescaling) 0 1 0 clk t2s /8 (from prescaler) 0 1 1 clk t2s /32 (from prescaler) 1 0 0 clk t2s /64 (from prescaler) 1 0 1 clk t2s /128 (from prescaler) 1 1 0 clk t 2 s /256 (from prescaler) 1 1 1 clk t 2 s /1024 (from prescaler) bit 7 6 5 4 3 2 1 0 tcnt2[7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ocr2a[7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
159 7682c?auto?04/08 at90can32/64/128 the output compare register a contains an 8-bit val ue that is continuously compared with the counter value (tcnt2). a match can be used to gener ate an output compare interrupt, or to generate a waveform output on the oc2a pin. 14.10 asynchronous operation of the timer/counter2 14.10.1 asynchronous status register ? assr ? bit 7..5 ? reserved bits these bits are reserved for future use. ? bit 4 ? exclk: enable external clock input when exclk is written to one, and asynchronous cloc k is selected, the external clock input buffer is enabled and an external clock can be inpu t on timer oscillator 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be don e before asynchronous operation is selected. note that the crystal oscillator will onl y run when this bit is zero. ? bit 3 ? as2: asynchronous timer/counter2 when as2 is written to zero, timer/counter2 is cloc ked from the i/o clock, clk i/o and the crystal oscillator connected to the timer/counter2 oscillat or (tosc) does nor run. when as2 is written to one, timer/counter2 is clocked from a crystal os cillator connected to the timer/counter2 oscillator (tosc) or from external clock on tosc1 d epending on exclk setting. when the value of as2 is changed, the contents of tcnt2, ocr 2a, and tccr2a might be corrupted. ? bit 2 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcn t2 is written, this bit becomes set. when tcnt2 has been updated from the temporary stor age register, this bit is cleared by hard- ware. a logical zero in this bit indicates that tcn t2 is ready to be updated with a new value. ? bit 1 ? ocr2ub: output compare register2 update bu sy when timer/counter2 operates asynchronously and ocr 2a is written, this bit becomes set. when ocr2a has been updated from the temporary stor age register, this bit is cleared by hard- ware. a logical zero in this bit indicates that ocr 2a is ready to be updated with a new value. ? bit 0 ? tcr2ub: timer/counter control register2 up date busy when timer/counter2 operates asynchronously and tcc r2a is written, this bit becomes set. when tccr2a has been updated from the temporary sto rage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. if a write is performed to any of the three timer/c ounter2 registers while its update busy flag is set, the updated value might get corrupted and caus e an unintentional interrupt to occur. the mechanisms for reading tcnt2, ocr2a, and tccr2a are different. when reading tcnt2, the actual timer value is read. when reading ocr2a or tccr2a, the value in the tem- porary storage register is read. bit 7 6 5 4 3 2 1 0 ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub assr read/write r r r r/w r/w r r r initial value 0 0 0 0 0 0 0 0
160 7682c?auto?04/08 at90can32/64/128 14.10.2 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some c onsiderations must be taken. ? warning: when switching between asynchronous and s ynchronous clocking of timer/counter2, the timer registers tcnt2, ocr2a, a nd tccr2a might be corrupted. a safe procedure for switching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2a and toie2. b. select clock source by setting as2 and exclk as a ppropriate. c. write new values to tcnt2, ocr2a, and tccr2a. d. to switch to asynchronous operation: wait for tcn 2ub, ocr2ub, and tcr2ub. e. clear the timer/counter2 interrupt flags. f. enable interrupts, if needed. ? the oscillator is optimized for use with a 32.768 khz watch crystal. the cpu main clock frequency must be more than four times the oscillat or or external clock frequency. ? when writing to one of the registers tcnt2, ocr2a, or tccr2a, the value is transferred to a temporary register, and latched after two positiv e edges on tosc1. the user should not write a new value before the contents of the tempor ary register have been transferred to its destination. each of the three mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not dis turb an ocr2a write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented. ? when entering power-save or extended standby mode after having written to tcnt2, ocr2a, or tccr2a, the user must wait until the writ ten register has been updated if timer/counter2 is used to wake up the device. other wise, the mcu will enter sleep mode before the changes are effective. this is particula rly important if the output compare2 interrupt is used to wake up the device, since the output compare function is disabled during writing to ocr2a or tcnt2. if the write cycle is no t finished, and the mcu enters sleep mode before the ocr2ub bit returns to zero, the dev ice will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up fr om power-save or extended standby mode, precautions must be taken if the user wants t o re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re- entering sleep mode is less than one tosc1 cycle, t he interrupt will not occur, and the device will fail to wake up. if the user is in doub t whether the time before re-entering power- save mode is sufficient, the following algorithm ca n be used to ensure that one tosc1 cycle has elapsed: a. write a value to tccr2a, tcnt2, or ocr2a. b. wait until the corresponding update busy flag in assr returns to zero. c. enter power-save or adc noise reduction mode. ? when the asynchronous operation is selected, the 3 2.768 khz oscillator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user s hould be aware of the fact that this oscillator might take as long as one second to stab ilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/counter2 registers must be considered lost after a wake-up from power-down or standby mode due to un stable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the tosc1 pin.
161 7682c?auto?04/08 at90can32/64/128 ? description of wake up from power-save mode when t he timer is clocked asynchronously: when the interrupt condition is met, the wake up pr ocess is started on the following cycle of the timer clock, that is, the timer is always advan ced by at least one before the processor can read the counter value. after wake-up, the mcu is h alted for four cycles, it executes the interrupt routine, and resumes execution from the i nstruction following sleep. ? reading of the tcnt2 register shortly after wake-u p from power-save may give an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt2 must be done through a register synchronized to the interna l i/o clock domain. synchronization takes place for every rising tosc1 edge. when waking up f rom power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the prev ious value (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: a. write any value to either of the registers ocr2a or tccr2a. b. wait for the corresponding update busy flag to be cleared. c. read tcnt2. ? during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus on e timer cycle. the timer is therefore advanced by at least one before the processor can r ead the timer value causing the setting of the interrupt flag. the output compare pin is chang ed on the timer clock and is not synchronized to the processor clock. 14.10.3 timer/counter2 interrupt mask register ? timsk2 ? bit 7..2 ? reserved bits these bits are reserved for future use. ? bit 1 ? ocie2a: timer/counter2 output compare matc h a interrupt enable when the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled . the corresponding interrupt is executed if a compare match in timer/counter2 occurs, i.e., when the ocf2a bit is set in the timer/counter2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt e nable when the toie2 bit is written to one and the i-bit in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the c orresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the t ov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. 14.10.4 timer/counter2 interrupt flag register ? tif r2 bit 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ocie2a toie2 timsk2 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ocf2a tov2 tifr2 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0
162 7682c?auto?04/08 at90can32/64/128 ? bit 7..2 ? reserved bits these bits are reserved for future use. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occ urs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when executing the corresponding interrupt handling vector. altern atively, ocf2a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2 (tim er/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter 2 compare match interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs i n timer/counter2. tov2 is cleared by hard- ware when executing the corresponding interrupt han dling vector. alternatively, tov2 is cleared by writing a logic one to the flag. when the sreg i -bit, toie2a (timer/counter2 overflow inter- rupt enable), and tov2 are set (one), the timer/cou nter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 chang es counting direction at 0x00. 14.11 timer/counter2 prescaler figure 14-13. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk io . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked from the tosc oscillator or tosc1 pin. this enables use of timer/counter2 as a real time counter (rtc). a crystal can then be connected between the tosc1 a nd tosc2 pins to serve as an indepen- dent clock source for timer/counter2. the oscillato r is optimized for use with a 32.768 khz crystal. setting as2 and resetting exclk enables th e tosc oscillator. 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 psr2 clear clk t2 0 1 tosc2 exclk 0 1 as2 exclk 32 khz oscillator enable tosc1
163 7682c?auto?04/08 at90can32/64/128 figure 14-14. timer/counter2 crystal oscillator connections a external clock can also be used using tosc1 as in put. setting as2 and exclk enables this configuration. figure 14-15. timer/counter2 external clock connections for timer/counter2, the possible prescaled selectio ns are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psr2 bit in gtccr resets the prescaler. this allows the user to operate with a pre- dictable prescaler. 14.11.1 general timer/counter control register ? gtc cr ? bit 1 ? psr2: prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is written when timer/counter2 is operating in asynchronous mode, the bit will remain one until the prescaler h as been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the descri ption of the ?bit 7 ? tsm: timer/counter syn- chronization mode? on page 98 for a description of the timer/counter synchroniza tion mode. tosc2 tosc1 gnd 12 - 22 pf 12 - 22 pf 32.768 khz tosc2 tosc1 nc external clock signal bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ? psr2 psr310 gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0
164 7682c?auto?04/08 at90can32/64/128 15. output compare modulator - ocm 15.1 overview many register and bit references in this section ar e written in general form. ? a lower case ?n? replaces the timer/counter number , in this case 0 and 1. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. ? a lower case ?x? replaces the output compare unit channel, in this case a or c. however, when using the register or bit defines in a program , the precise form must be used, i.e., ocr0a for accessing timer/counter0 output compare c hannel a value and so on. the output compare modulator (ocm) allows generatio n of waveforms modulated with a carrier frequency. the modulator uses the outputs from the output compare unit c of the 16-bit timer/counter1 and the output compare unit of the 8 -bit timer/counter0. for more details about these timer/counters see ?16-bit timer/counter (timer/counter1 and timer/cou nter3)? on page 113 and ?8-bit timer/counter0 with pwm? on page 99 . figure 15-1. output compare modulator, block diagram when the modulator is enabled, the two output compa re channels are modulated together as shown in the block diagram ( figure 15-1 ). 15.2 description the output compare unit 1c and output compare unit 0a shares the pb7 port pin for output. the outputs of the output compare units (oc1c and o c0a) overrides the normal portb7 register when one of them is enabled (i.e., when co mnx1:0 is not equal to zero). when both oc1c and oc0a are enabled at the same time, the mod ulator is automatically enabled. when the modulator is enabled the type of modulatio n (logical and or or) can be selected by the portb7 register. note that the ddrb7 controls t he direction of the port independent of the comnx1:0 bit setting. the functional equivalent schematic of the modulato r is shown on figure 15-2 . the schematic includes part of the timer/counter units and the po rt b pin 7 output driver circuit. oc1c pin oc0a / oc1c / pb7 timer/counter 1 timer/counter 0 oc0a
165 7682c?auto?04/08 at90can32/64/128 figure 15-2. output compare modulator, schematic 15.2.1 timing example figure 15-3 illustrates the modulator in action. in this examp le the timer/counter1 is set to oper- ate in fast pwm mode (non-inverted) and timer/count er0 uses ctc waveform mode with toggle compare output mode (comnx1:0 = 1). figure 15-3. output compare modulator, timing diagram in this example, timer/counter0 provides the carrie r, while the modulating signal is generated by the output compare unit c of the timer/counter1. portb7 ddrb7 d q d q pin databus com0a1 com0a0 oc0a / oc1c / pb7 com1c1 com1c0 modulator 1 0 oc1c d q oc0a d q (from t/c1 waveform generator) (from t/c0 waveform generator) 0 1 vcc 1 2 oc0a (ctc mode) oc1c (fpwm mode) pb7 (portb7 = 0) pb7 (portb7 = 1) (period) 3 clk i/o
166 7682c?auto?04/08 at90can32/64/128 15.2.2 resolution of the pwm signal the resolution of the pwm signal (oc1c) is reduced by the modulation. the reduction factor is equal to the number of system clock cycles of one p eriod of the carrier (oc0a). in this example the resolution is reduced by a factor of two. the r eason for the reduction is illustrated in figure 15-3 at the second and third period of the pb7 output w hen portb7 equals zero. the period 2 high time is one cycle longer than the period 3 hig h time, but the result on the pb7 output is equal in both periods.
167 7682c?auto?04/08 at90can32/64/128 16. serial peripheral interface ? spi the serial peripheral interface (spi) allows high-s peed synchronous data transfer between the at90can32/64/128 and peripheral devices or between several avr devices. the at90can32/64/128 spi includes the following feature s: 16.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode figure 16-1. spi block diagram (1) note: 1. refer to figure 1-2 on page 5 , and table 9-6 on page 76 for spi pin placement. spi2x spi2x divider /2/4/8/16/32/64/128 clk io
168 7682c?auto?04/08 at90can32/64/128 the interconnection between master and slave cpus w ith spi is shown in figure 16-2 . the sys- tem consists of two shift registers, and a master c lock generator. the spi master initiates the communication cycle when pulling low the slave sele ct ss pin of the desired slave. master and slave prepare the data to be sent in their respecti ve shift registers, and the master generates the required clock pulses on the sck line to interc hange data. data is always shifted from mas- ter to slave on the master out ? slave in, mosi, li ne, and from slave to master on the master in ? slave out, miso, line. after each data packet, th e master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communicati on can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte, the s pi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enab le bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may up date the contents of the spi data register, spdr, but the data will not be shifted ou t by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 16-2. spi master-slave interconnection the system is single buffered in the transmit direc tion and double buffered in the receive direc- tion. this means that bytes to be transmitted canno t be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next cha racter has been completely shifted in. oth- erwise, the first byte is lost. in spi slave mode, the control logic will sample th e incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f clkio /4. shift enable
169 7682c?auto?04/08 at90can32/64/128 when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 16-1 . for more details on automatic port overrides, ref er to ?alternate port functions? on page 71 . note: 1. see ?alternate functions of port b? on page 76 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. table 16-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input
170 7682c?auto?04/08 at90can32/64/128 ddr_spi in the examples must be replaced by the act ual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be repla ced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb2, replace dd_mosi with ddb2 and ddr_spi with ddrb. note: 1. the example code assumes that the part speci fic header file is included. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 171 7682c?auto?04/08 at90can32/64/128 the following code examples show how to initialize the spi as a slave and how to perform a simple reception. note: 1. the example code assumes that the part speci fic header file is included. 16.2 ss pin functionality 16.2.1 slave mode when the spi is configured as a slave, the slave se lect (ss) pin is always input. when ss is held low, the spi is activated, and miso becomes an output if configured so by the user. all other pins are inputs. when ss is driven high, all pins are inputs, and the spi i s passive, which assembly code example (1) spi_slaveinit: ; set miso output, all others input ldi r17,(1< 172 7682c?auto?04/08 at90can32/64/128 means that it will not receive incoming data. note that the spi logic will be reset once the ss pin is driven high. the ss pin is useful for packet/byte synchronization to k eep the slave bit counter synchronous with the master clock generator. when the ss pin is driven high, the spi slave will immediately reset the send and receive logic, and drop any part ially received data in the shift register. 16.2.2 master mode when the spi is configured as a master (mstr in spc r is set), the user can determine the direction of the ss pin. if ss is configured as an output, the pin is a general o utput pin which does not affect the spi system. typically, the pin will be driving the ss pin of the spi slave. if ss is configured as an input, it must be held high to ensure master spi operation. if the ss pin is driven low by peripheral circuitry when the spi is configured as a master with the ss pin defined as an input, the spi system interprets this as another master selecting the spi as a slave and starting to send data to it. to avoid bus contention, the spi system takes the following actions: 1. the mstr bit in spcr is cleared and the spi syste m becomes a slave. as a result of the spi becoming a slave, the mosi and sck pins bec ome inputs. 2. the spif flag in spsr is set, and if the spi inte rrupt is enabled, and the i-bit in sreg is set, the interrupt routine will be executed. thus, when interrupt-driven spi transmission is use d in master mode, and there exists a possi- bility that ss is driven low, the interrupt should always check t hat the mstr bit is still set. if the mstr bit has been cleared by a slave select, it mus t be set by the user to re-enable spi master mode. 16.2.3 spi control register ? spcr ? bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be executed if spif bit in the spsr register is set and if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enab led. this bit must be set to enable any spi operations. ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of th e data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to on e, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, bit 7 6 5 4 3 2 1 0 spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
173 7682c?auto?04/08 at90can32/64/128 and spif in spsr will become set. the user will the n have to set mstr to re-enable spi mas- ter mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when i dle. when cpol is written to zero, sck is low when idle. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is sum- marized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determin e if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 16-3 and figure 16-4 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 an d 0 these two bits control the sck rate of the device c onfigured as a master. spr1 and spr0 have no effect on the slave. the relationship between sc k and the clk io frequency f clkio is shown in the following table: table 16-2. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 16-3. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 16-4. relationship between sck and the oscillator frequen cy spi2x spr1 spr0 sck frequency 0 0 0 f clkio / 4 0 0 1 f clkio / 16 0 1 0 f clkio / 64 0 1 1 f clkio / 128 1 0 0 f clkio / 2 1 0 1 f clkio / 8 1 1 0 f clkio / 32 1 1 1 f clkio / 64
174 7682c?auto?04/08 at90can32/64/128 16.2.4 spi status register ? spsr ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag i s set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if s s is an input and is driven low when the spi is in master mode, this will also set the spif flag. s pif is cleared by hardware when executing the corresponding interrupt handling vector. alternativ ely, the spif bit is cleared by first reading the spi status register with spif set, then accessing t he spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first re ading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the at90can32/64/12 8 and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (s ck frequency) will be doubled when the spi is in master mode (see table 16-4 ). this means that the minimum sck period will be t wo cpu clock periods. when the spi is configured as slave, the spi is only guaranteed to work at f clkio /4 or lower. the spi interface on the at90can32/64/128 is also u sed for program memory and eeprom downloading or uploading. see page 347 for serial programming and verification. 16.2.5 spi data register ? spdr ? bits 7:0 - spd7:0: spi data the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the regis- ter causes the shift register receive buffer to be read. 16.3 data modes there are four combinations of sck phase and polari ty with respect to serial data, which are determined by control bits cpha and cpol. the spi d ata transfer formats are shown in figure 16-3 and figure 16-4 . data bits are shifted out and latched in on oppos ite edges of the sck sig- bit 7 6 5 4 3 2 1 0 spif wcol ? ? ? ? ? spi2x spsr read/write r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined
175 7682c?auto?04/08 at90can32/64/128 nal, ensuring sufficient time for data signals to s tabilize. this is clearly seen by summarizing table 16-2 and table 16-3 , as done below: figure 16-3. spi transfer format with cpha = 0 figure 16-4. spi transfer format with cpha = 1 table 16-5. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1)
176 7682c?auto?04/08 at90can32/64/128 17. usart (usart0 and usart1) the universal synchronous and asynchronous serial r eceiver and transmitter (usart) is a highly flexible serial communication device. the ma in features are: 17.1 features ? full duplex operation (independent serial receive a nd transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data b its and 1 or 2 stop bits ? odd or even parity generation and parity check supp orted by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete, tx data r egister empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode 17.2 overview many registers and bit references in this section a re written in general form. ? a lower case ?n? replaces the usart number, in thi s case 0 or 1. however, when using the register or bit defines in a program, the precise f orm must be used, i.e., udr0 for accessing usart0 i/o data value and so on. 17.3 dual usart the at90can32/64/128 has two usart?s, usart0 and us art1. the functionality for both usart?s is described below. usart0 and usart1 have different i/o registers as shown in ?register summary? on page 384 . a simplified block diagram of the usartn transmitte r is shown in figure 17-1 . cpu accessible i/o registers and i/o pins are shown in bold.
177 7682c?auto?04/08 at90can32/64/128 figure 17-1. usartn block diagram (1) note: 1. refer to figure 1-2 on page 5 , table 9-15 on page 83 , and table 9-10 on page 79 for usartn pin placement. the dashed boxes in the block diagram separate the three main parts of the usartn (listed from the top): clock generator, transmitter and rec eiver. control registers are shared by all units. the clock generation logic consists of synch ronization logic for external clock input used by synchronous slave operation, and the baud rate g enerator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the transmi tter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame for- mats. the write buffer allows a continuous transfer of data without any delay between frames. the receiver is the most complex part of the usartn module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, cont rol logic, a shift register and a two level receive buffer (udrn). the receiver supports the sa me frame formats as the transmitter, and can detect frame error, data overrun and parity err ors. parity generator ubrr n[h:l] udr n (transmit) ucsran ucsrbn ucsrcn baud rate generator transmit shift register receive shift register rxdn txdn pin control udrn (receive) pin control xckn data recovery clock recovery pin control tx control rx control parity checker data bus clkio sync logic clock generator transmitter receiver
178 7682c?auto?04/08 at90can32/64/128 17.4 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usartn supports four modes of clock operation: norm al asynchronous, double speed asyn- chronous, master synchronous and slave synchronous mode. the umseln bit in usartn control and status register c (ucsrnc) selects betw een asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. when using synchronous mode (umsel n = 1), the data direction register for the xckn pin (ddr_xckn) controls whether the cl ock source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. figure 17-2 shows a block diagram of the clock generation logi c. figure 17-2. usartn clock generation logic, block diagram signal description: txn clk transmitter clock (internal signal). rxn clk receiver base clock (internal signal). xn cki input from xck pin (internal signal). used for sync hronous slave operation. xn cko clock output to xck pin (internal signal). used for synchronous master operation. f clk io system i/o clock frequency. 17.4.1 internal clock generation ? baud rate generat or internal clock generation is used for the asynchron ous and the synchronous master modes of operation. the description in this section refers t o figure 17-2 . the usartn baud rate register (ubrrn) and the down- counter connected to it function as a programmable prescaler or baud rate generator. the down-counter, running at system clock ( f clk io ), is loaded with the ubrrn value each time the cou nter has counted down to zero or when the ubrrnl register is written. a clock is gen erated each time the counter reaches zero. this clock is the baud rate generator clock output (= f clk io /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator output is used directly by the receiver?s clock and data recovery units. however, the recovery prescaling down-counter /2 ubrrn /4 /2 sync register clk xckn pin txn clk u2xn umseln ddr_xckn 0 1 0 1 xn cki xn cko ddr_xckn rxn clk 0 1 1 0 edge detector ucpoln io ubrrn+1 f clk io
179 7682c?auto?04/08 at90can32/64/128 units use a state machine that uses 2, 8 or 16 stat es depending on mode set by the state of the umseln, u2xn and ddr_xckn bits. table 17-1 contains equations for calculating the baud rate ( in bits per second) and for calculat- ing the ubrrn value for each mode of operation usin g an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps). f clk io system i/o clock frequency. ubrrn contents of the ubrrnh and ubrrnl registers, (0-409 5). some examples of ubrrn values for some system clock frequencies are found in table 17-9 (see page 199 ). 17.4.2 double speed operation (u2x) the transfer rate can be doubled by setting the u2x n bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the bau d rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. n ote however that the receiver will in this case only use half the number of samples (reduced f rom 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate s etting and system clock are required when this mode is used. for the transmitter, there are n o downsides. 17.4.3 external clock external clocking is used by the synchronous slave modes of operation. the description in this section refers to figure 17-2 for details. external clock input from the xckn pin is sampled b y a synchronization register to minimize the chance of meta-stability. the output from the synch ronization register must then pass through an edge detector before it can be used by the trans mitter and receiver. this process intro- duces a two cpu clock period delay and therefore th e maximum external xckn clock frequency is limited by the following equation: table 17-1. equations for calculating baud rate register settin g operating mode equation for calculating baud rate (1) equation for calculating ubrrn value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f clkio 16 ubrr n 1 + ( ) ------------------------------------------ = ubrr n f clkio 16 baud ------------------------ 1 ? = baud f clkio 8 ubrr n 1 + ( ) --------------------------------------- = ubrr n f clkio 8 baud -------------------- 1 ? = baud f clkio 2 ubrr n 1 + ( ) --------------------------------------- = ubrr n f clkio 2 baud -------------------- 1 ? = f xckn f clkio 4 ---------------- <
180 7682c?auto?04/08 at90can32/64/128 note that f clk io depends on the stability of the system clock sourc e. it is therefore recommended to add some margin to avoid possible loss of data d ue to frequency variations. 17.4.4 synchronous clock operation when synchronous mode is used (umseln = 1), the xck n pin will be used as either clock input (slave) or clock output (master). the dependency be tween the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data outpu t (txdn) is changed. figure 17-3. synchronous mode xckn timing. the ucpoln bit ucrsnc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 17-3 shows, when ucpoln is zero the data will be change d at rising xckn edge and sampled at falling xckn edg e. if ucpoln is set, the data will be changed at falling xckn edge and sampled at rising xckn edge. 17.5 serial frame a serial frame is defined to be one character of da ta bits with synchronization bits (start and stop bits), and optionally a parity bit for error checki ng. 17.5.1 frame formats the usartn accepts all 30 combinations of the follo wing as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the l east significant data bit. then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. if enabled, the parity bi t is inserted after the data bits, before the stop bi ts. when a complete frame is transmitted, it can be directly followed by a new frame, or the communi cation line can be set to an idle (high) state. figure 17-4 illustrates the possible combinations of the frame formats. bits inside brackets are optional. rxdn / txdn xckn rxdn / txdn xckn ucpoln = 0 ucpoln = 1 sample sample
181 7682c?auto?04/08 at90can32/64/128 figure 17-4. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txd n). an idle line must be high. the frame format used by the usartn is set by the u cszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt all o ngoing communication for both the receiver and transmitter. the usartn character size (ucszn2:0) bits select th e number of data bits in the frame. the usartn parity mode (upmn1:0) bits enable and set th e type of parity bit. the selection between one or two stop bits is done by the usartn stop bit select (usbsn) bit. the receiver ignores the second stop bit. an fen (frame error) w ill therefore only be detected in the cases where the first stop bit is zero. 17.5.2 parity bit calculation the parity bit is calculated by doing an exclusive- or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the relatio n between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. 17.6 usart initialization the usartn has to be initialized before any communi cation can take place. the initialization process normally consists of setting the baud rate, setting frame format and enabling the trans- mitter or the receiver depending on the usage. for interrupt driven usartn operation, the global interrupt flag should be cleared (and interr upts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registe rs are changed. the txcn flag can be used to check that the transmitter has completed all tra nsfers, and the rxcn flag can be used to 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = =
182 7682c?auto?04/08 at90can32/64/128 check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is wr itten) if it is used for this purpose. the following simple usart0 initialization code exa mples show one assembly and one c func- tion that are equal in functionality. the examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. t he baud rate is given as a function parameter. for the assembly code, the baud rate parameter is a ssumed to be stored in the r17:r16 registers. note: 1. the example code assumes that the part speci fic header file is included. more advanced initialization routines can be made t hat include frame format as parameters, dis- able interrupts and so on. however, many applicatio ns use a fixed setting of the baud and control registers, and for these types of applicati ons the initialization code can be placed directly in the main routine, or be combined with initializa tion code for other i/o modules. 17.7 data transmission ? usart transmitter the usartn transmitter is enabled by setting the tr ansmit enable (txenn) bit in the ucsrnb register. when the transmitter is enabled, the norm al port operation of the txdn pin is overrid- den by the usartn and given the function as the tra nsmitter?s serial output. the baud rate, mode of operation and frame format must be set up o nce before doing any transmissions. if syn- assembly code example (1) usart0_init: ; set baud rate sts ubrr0h, r17 sts ubrr0l, r16 ; set frame format: 8data, no parity & 2 stop bits ldi r16, (0<>8); ubrr0l = ( unsigned char ) baud; /* set frame format: 8data, no parity & 2 stop bits */ ucsr0c = (0< 183 7682c?auto?04/08 at90can32/64/128 chronous operation is used, the clock on the xckn p in will be overridden and used as transmission clock. 17.7.1 sending frames with 5 to 8 data bit a data transmission is initiated by loading the tra nsmit buffer with the data to be transmitted. the cpu can load the transmit buffer by writing to the udrn i/o location. the buffered data in the transmit buffer will be moved to the shift register when the shift register is ready to send a new frame. the shift register is loaded with new data i f it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. when the shift register is loaded with new data, it will transfer one complete frame at the rate given by the baud register, u2xn bit or by xckn depending on mode of operation. the following code examples show a simple usart0 tr ansmit function based on polling of the data register empty (udre0) flag. when using frames with less than eight bits, the most signif- icant bits written to the udr0 are ignored. the usa rt0 has to be initialized before the function can be used. for the assembly code, the data to be sent is assumed to be stored in register r16 . note: 1. the example code assumes that the part speci fic header file is included. the function simply waits for the transmit buffer t o be empty by checking the udre0 flag, before loading it with new data to be transmitted. if the data register empty interrupt is utilized, the interrupt routine writes the data into the buffer. assembly code example (1) usart0_transmit: ; wait for empty transmit buffer lds r17, ucsr0a sbrs r17, udre0 rjmp usart0_transmit ; put data (r16) into buffer, sends the data sts udr0, r16 ret c code example (1) void usart0_transmit ( unsigned char data) { /* wait for empty transmit buffer */ while ( ! ( ucsra0 & (1< 184 7682c?auto?04/08 at90can32/64/128 17.7.2 sending frames with 9 data bit if 9-bit characters are used (ucszn = 7), the ninth bit must be written to the txb8n bit in ucs- rnb before the low byte of the character is written to udrn. the following code examples show a transmit function that handles 9-bit characters. for the assembly code, the data to be sent is assumed to be stored in registers r17:r16. notes: 1. these transmit functions are written to be general functions. they can be optimized if the con - tents of the ucsr0b is static. for example, only th e txb80 bit of the ucsrb0 register is used after initialization. 2. the example code assumes that the part specific h eader file is included. the ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for e xample synchronization. 17.7.3 transmitter flags and interrupts the usartn transmitter has two flags that indicate its state: usart data register empty (udren) and transmit complete (txcn). both flags ca n be used for generating interrupts. assembly code example (1)(2) usart0_transmit: ; wait for empty transmit buffer lds r18, ucsr0a sbrs r18, udre0 rjmp usart0_transmit ; copy 9th bit from r17-bit0 to txb80 via t-bit of sr eg lds r18, ucsr0b bst r17, 0 bld r18, txb80 sts ucsr0b, r18 ; put lsb data (r16) into buffer, sends the data sts udr0, r16 ret c code example (1)(2) void usart0_transmit ( unsigned int data) { /* wait for empty transmit buffer */ while ( !( ucsr0a & (1< 185 7682c?auto?04/08 at90can32/64/128 the data register empty (udren) flag indicates whet her the transmit buffer is ready to receive new data. this bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet be en moved into the shift register. for compat- ibility with future devices, always write this bit to zero when writing the ucsrna register. when the data register empty interrupt enable (udri en) bit in ucsrbn is written to one, the usartn data register empty interrupt will be execut ed as long as udren is set (provided that global interrupts are enabled). udren is cleared by writing udrn. when interrupt-driven data transmission is used, the data register empty inter rupt routine must either write new data to udrn in order to clear udren or disable the data re gister empty interrupt, otherwise a new interrupt will occur once the interrupt routine ter minates. the transmit complete (txcn) flag bit is set one wh en the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer. the txcn flag bit is automatically cleared when a t ransmit complete interrupt is executed, or it can be cleared by writing a one to its bit location . the txcn flag is useful in half-duplex commu- nication interfaces (like the rs-485 standard), whe re a transmitting application must enter receive mode and free the communication bus immedia tely after completing the transmission. when the transmit complete interrupt enable (txcien ) bit in ucsrnb is set, the usartn transmit complete interrupt will be executed when t he txcn flag becomes set (provided that global interrupts are enabled). when the transmit c omplete interrupt is used, the interrupt han- dling routine does not have to clear the txcn flag, this is done automatically when the interrupt is executed. 17.7.4 parity generator the parity generator calculates the parity bit for the serial frame data. when parity bit is enabled (upmn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. 17.7.5 disabling the transmitter the disabling of the transmitter (setting the txenn to zero) will not become effective until ongo- ing and pending transmissions are completed, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. when disabled, the transmitter will no longer override the txdn pin. 17.8 data reception ? usart receiver the usartn receiver is enabled by writing the recei ve enable (rxenn) bit in the ucsrnb register to one. when the receiver is enabled, the normal pin operation of the rxdn pin is over- ridden by the usartn and given the function as the receiver?s serial input. the baud rate, mode of operation and frame format must be set up o nce before any serial reception can be done. if synchronous operation is used, the clock o n the xckn pin will be used as transfer clock. 17.8.1 receiving frames with 5 to 8 data bits the receiver starts data reception when it detects a valid start bit. each bit that follows the start bit will be sampled at the baud rate or xckn clock, and shifted into the receive shift register until the first stop bit of a frame is received. a second stop bit will be ignored by the receiver. when the first stop bit is received, i.e., a comple te serial frame is present in the receive shift register, the contents of the shift register will b e moved into the receive buffer. the receive buffer can then be read by reading the udrn i/o loc ation.
186 7682c?auto?04/08 at90can32/64/128 the following code example shows a simple usart0 re ceive function based on polling of the receive complete (rxc0) flag. when using frames wit h less than eight bits the most significant bits of the data read from the udr0 will be masked to zero. the usart0 has to be initialized before the function can be used. note: 1. the example code assumes that the part speci fic header file is included. the function simply waits for data to be present in the receive buffer by checking the rxc0 flag, before reading the buffer and returning the value. 17.8.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bi t must be read from the rxb8n bit in ucs- rnb before reading the low bits from the udrn. this rule appl ies to the fen, dorn and upen status flags as well. read status from ucsrna, then data from udrn. reading the udrn i/o location will change the state of the receive buffe r fifo and consequently the txb8n, fen, dorn and upen bits, which all are stored in the fif o, will change. assembly code example (1) usart0_receive: ; wait for data to be received lds r18, ucsr0a sbrs r18, rxc0 rjmp usart0_receive ; get and return received data from buffer lds r16, udr0 ret c code example (1) unsigned char usart0_receive ( void ) { /* wait for data to be received */ while ( ! (ucsr0a & (1< 187 7682c?auto?04/08 at90can32/64/128 the following code example shows a simple usart0 re ceive function that handles both nine bit characters and the status bits. note: 1. the example code assumes that the part speci fic header file is included. the receive function example reads all the i/o regi sters into the register file before any com- putation is done. this gives an optimal receive buf fer utilization since the buffer location read will be free to accept new data as early as possible. assembly code example (1) usart0_receive: ; wait for data to be received lds r18, ucsr0a sbrs r18, rxc0 rjmp usart0_receive ; get status and 9th bit, then data from buffer lds r17, ucsr0b lds r16, udr0 ; if error, return -1 andi r18, (1<> 1) & 0x01; return ((resh << 8) | resl); }
188 7682c?auto?04/08 at90can32/64/128 17.8.3 receive complete flag and interrupt the usartn receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicates if there are unread data present in the receive buffer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and consequently the rxcn bit will become zero. when the receive complete interrupt enable (rxcien) in ucsrnb is set, the usartn receive complete interrupt will be executed as long as the rxcn flag is set (provided that glo- bal interrupts are enabled). when interrupt-driven data reception is used, the receive complete routine must read the received data from udrn in or der to clear the rxcn flag, otherwise a new interrupt will occur once the interrupt routine ter minates. 17.8.4 receiver error flags the usartn receiver has three error flags: frame er ror (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer togethe r with the frame for which they indicate the error status. due to the buffering of the error fla gs, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location changes the buffer read location. another equality for the error flags is that they can not b e altered by software doing a write to the flag location. however, all flags must be set to zero wh en the ucsrna is written for upward compat- ibility of future usart implementations. none of th e error flags can generate interrupts. the frame error (fen) flag indicates the state of t he first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break c onditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrnc since the receiver ignores all, except for the first, stop bits. for compatibility with fu ture devices, always set this bit to zero when writ - ing to ucsrna. the data overrun (dorn) flag indicates data loss du e to a receiver buffer full condition. a data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last re ad from udrn, and the next frame read from udrn. for compatibility with future devices, always write this bit to zero when writing to ucs- rna. the dorn flag is cleared when the frame receiv ed was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the nex t frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 181 and ?parity checker? on page 188 . 17.8.5 parity checker the parity checker is active when the high usartn p arity mode (upmn1) bit is set. type of parity check to be performed (odd or even) is selec ted by the upmn0 bit. when enabled, the parity checker calculates the parity of the data bi ts in incoming frames and compares the result with the parity bit from the serial frame. the resu lt of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error.
189 7682c?auto?04/08 at90can32/64/128 the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was ena bled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 17.8.6 disabling the receiver in contrast to the transmitter, disabling of the re ceiver will be immediate. data from ongoing receptions will therefore be lost. when disabled (i .e., the rxenn is set to zero) the receiver will no longer override the normal function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining da ta in the buffer will be lost 17.8.7 flushing the receive buffer the receiver buffer fifo will be flushed when the r eceiver is disabled, i.e., the buffer will be emptied of its contents. unread data will be lost. if the buffer has to be flushed during normal operation, due to for instance an error condition, read the udrn i/o location until the rxcn flag is cleared. the following code example shows how to flush the r eceive buffer. note: 1. the example code assumes that the part speci fic header file is included. 17.9 asynchronous data reception the usartn includes a clock recovery and a data rec overy unit for handling asynchronous data reception. the clock recovery logic is used for syn chronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data recovery logic sam- ples and low pass filters each incoming bit, thereb y improving the noise immunity of the receiver. the asynchronous reception operational ra nge depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frame s, and the frame size in number of bits. 17.9.1 asynchronous clock recovery the clock recovery logic synchronizes internal cloc k to the incoming serial frames. figure 17-5 illustrates the sampling process of the start bit o f an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the hor- assembly code example (1) usart0_flush: lds r16, ucsr0a sbrs r16, rxc0 ret lds r16, udr0 rjmp usart0_flush c code example (1) void usart0_flush ( void ) { unsigned char dummy; while (ucsr0a & (1< 190 7682c?auto?04/08 at90can32/64/128 izontal arrows illustrate the synchronization varia tion due to the sampling process. note the larger time variation when using the double speed m ode (u2xn = 1) of operation. samples denoted zero are samples done when the rxdn line is idle (i.e., no communication activity). figure 17-5. start bit sampling when the clock recovery logic detects a high (idle) to low (start) transition on the rxdn line, the start bit detection sequence is initiated. let samp le 1 denote the first zero-sample as shown in the figure. the clock recovery logic then uses samp les 8, 9, and 10 for normal mode, and sam- ples 4, 5, and 6 for double speed mode (indicated w ith sample numbers inside boxes on the figure), to decide if a valid start bit is received . if two or more of these three samples have logica l high levels (the majority wins), the start bit is r ejected as a noise spike and the receiver starts looking for the next high to low-transition. if how ever, a valid start bit is detected, the clock reco v- ery logic is synchronized and the data recovery can begin. the synchronization process is repeated for each start bit. 17.9.2 asynchronous data recovery when the receiver clock is synchronized to the star t bit, the data recovery can begin. the data recovery unit uses a state machine that has 16 stat es for each bit in normal mode and eight states for each bit in double speed mode. figure 17-6 shows the sampling of the data bits and the parity bit. each of the samples is given a numb er that is equal to the state of the recovery unit. figure 17-6. sampling of data and parity bit the decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the rec eived bit. the center samples are emphasized on the figure by having the sample number inside bo xes. the majority voting process is done as follows: if two or all three samples have high leve ls, the received bit is registered to be a logic 1. if two or all three samples have low levels, the re ceived bit is registered to be a logic 0. this majority voting process acts as a low pass filter f or the incoming signal on the rxdn pin. the recovery process is then repeated until a complete frame is received. including the first stop bit. note that the receiver only uses the first stop bit of a frame. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 start idle 0 0 bit 0 3 1 2 3 4 5 6 7 8 1 2 0 rxdn sample (u2xn = 0) sample (u2xn = 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 bit x 1 2 3 4 5 6 7 8 1 rxdn sample (u2xn = 0) sample (u2xn = 1)
191 7682c?auto?04/08 at90can32/64/128 figure 17-7 shows the sampling of the stop bit and the earlies t possible beginning of the start bit of the next frame. figure 17-7. stop bit sampling and next start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 value, the fram e error (fen) flag will be set. a new high to low transition indicating the start b it of a new frame can come right after the last of the bits used for majority voting. for normal speed mode, the first low level sample can be at point marked (a) in figure 17-7 . for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length. the early start bit detection influences the operational range of the receiver. 17.9.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud ra te of the receiver does not have a similar (see table 17-2 ) base frequency, the receiver will not be able to synchronize the frames to the start bit. the following equations can be used to calculate th e ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fas t is the ratio of the fastest incoming data rate tha t can be accepted in relation to the receiver baud rate. table 17-2 and table 17-3 list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has higher toleration of bau d rate variations. 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 stop 1 1 2 3 4 5 6 0/1 rxdn sample (u2xn = 0) sample (u2xn = 1) (a) (b) (c) r slow d 1 + ( ) s s 1 ? d s ? s f + + ------------------------------------------- = r fast d 2 + ( ) s d 1 + ( ) s s m + ----------------------------------- =
192 7682c?auto?04/08 at90can32/64/128 the recommendations of the maximum receiver baud ra te error was made under the assump- tion that the receiver and transmitter equally divi des the maximum total error. there are two possible sources for the receivers ba ud rate error. the receiver?s system clock (xtal) will always have some minor instability over the supply voltage range and the tempera- ture range. when using a crystal to generate the sy stem clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. t he baud rate generator can not always do an exact division of the system frequency to get the b aud rate wanted. in this case an ubrrn value that gives an acceptable low error can be used if p ossible. 17.10 multi-processor communication mode setting the multi-processor communication mode (mpc mn) bit in ucsrna enables a filtering function of incoming frames received by the usartn receiver. frames that do not contain address information will be ignored and not put int o the receive buffer. this effectively reduces the number of incoming frames that has to be handle d by the cpu, in a system with multiple mcus that communicate via the same serial bus. the transmitter is unaffected by the mpcmn setting, but has to be used differently when it is a part of a system utilizing the multi-processor communication mode. table 17-2. recommended maximum receiver baud rate error for no rmal speed mode (u2xn = 0) d # (data + parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 17-3. recommended maximum receiver baud rate error for do uble speed mode (u2xn = 1) d # (data + parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0
193 7682c?auto?04/08 at90can32/64/128 17.10.1 mpcm protocol if the receiver is set up to receive frames that co ntain 5 to 8 data bits, then the first stop bit ind i- cates if the frame contains data or address informa tion. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the first stop or the ninth bit ) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables seve ral slave mcus to receive data from a master mcu. this is done by first decoding an addre ss frame to find out which mcu has been addressed. if a particular slave mcu has been addre ssed, it will receive the following data frames as normal, while the other slave mcus will i gnore the received frames until another address frame is received. 17.10.2 using mpcm for an mcu to act as a master mcu, it can use a 9-b it character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txbn = 0) is being transmitted. the slave mcus mus t in this case be set to use a 9-bit charac- ter frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-processor communicati on mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all sl aves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determ ines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data frames un til a new address frame is received. the other slave mcus, which still have the mpcmn bi t set, will ignore the data frames. 5. when the last data frame is received by the addre ssed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame fro m master. the process then repeats from 2. using any of the 5- to 8-bit character frame format s is possible, but impractical since the receiver must change between using n and n+1 charac ter frame formats. this makes full- duplex operation difficult since the transmitter an d receiver use the same character size set- ting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the first stop bit is used for in dicating the frame type.
194 7682c?auto?04/08 at90can32/64/128 17.11 usart register description 17.11.1 usart0 i/o data register ? udr0 17.11.2 usart1 i/o data register ? udr1 ? bit 7:0 ? rxbn7:0: receive data buffer (read access) ? bit 7:0 ? txbn7:0: transmit data buffer (write access) the usartn transmit data buffer register and usartn receive data buffer registers share the same i/o address referred to as usartn data reg ister or udrn. the transmit data buffer register (txbn) will be the destination for data wr itten to the udrn register location. reading the udrn register location will return the contents of the receive data buffer register (rxbn). for 5-, 6-, or 7-bit characters the upper unused bi ts will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the ud ren flag in the ucsrna register is set. data written to udrn when the udren flag is not set , will be ignored by the usartn transmit- ter. when data is written to the transmit buffer, a nd the transmitter is enabled, the transmitter will load the data into the transmit shift register when the shift register is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fifo. th e fifo will change its state whenever the receive buffer is accessed. 17.11.3 usart0 control and status register a ? ucsr0 a 17.11.4 usart1 control and status register a ? ucsr1 a ? bit 7 ? rxcn: usartn receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and consequently the rxcn bi t will become zero. the rxcn flag can be used to generate a receive complete interrupt (see description of the rxcien bit). bit 7 6 5 4 3 2 1 0 rxb0[7:0] udr0 (read) txb0[7:0] udr0 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 rxb1[7:0] udr1 (read) txb1[7:0] udr1 (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 ucsr0a read/write r r/w r r r r r/w r/w initial value 0 0 1 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 ucsr1a read/write r r/w r r r r r/w r/w initial value 0 0 1 0 0 0 0 0
195 7682c?auto?04/08 at90can32/64/128 ? bit 6 ? txcn: usartn transmit complete this flag bit is set when the entire frame in the t ransmit shift register has been shifted out and there are no new data currently present in the tran smit buffer (udrn). the txcn flag bit is auto- matically cleared when a transmit complete interrup t is executed, or it can be cleared by writing a one to its bit location. the txcn flag can genera te a transmit complete interrupt (see descrip- tion of the txcien bit). ? bit 5 ? udren: usartn data register empty the udren flag indicates if the transmit buffer (ud rn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the ud rien bit). udren is set after a reset to indicate that the tra nsmitter is ready. ? bit 4 ? fen: frame error this bit is set if the next character in the receiv e buffer had a frame error when received. i.e., when the first stop bit of the next character in th e receive buffer is zero. this bit is valid until t he receive buffer (udrn) is read. the fen bit is zero when the stop bit of received data is one. always set this bit to zero when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is dete cted. a data overrun occurs when the receive buffer is full (two characters), it is a new charac ter waiting in the receive shift register, and a new start bit is detected. this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 2 ? upen: usartn parity error this bit is set if the next character in the receiv e buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when wr iting to ucsrna. ? bit 1 ? u2xn: double the usartn transmission speed this bit only has effect for the asynchronous opera tion. write this bit to zero when using syn- chronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous communicat ion. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcmn bit is written to one, all the incoming frames received by the usarnt receiver that do not contain address information will be ignored. the transmitter is una ffected by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 192 . 17.11.5 usart0 control and status register b ? ucsr0 b bit 7 6 5 4 3 2 1 0 rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 ucsr0b read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0
196 7682c?auto?04/08 at90can32/64/128 17.11.6 usart1 control and status register b ? ucsr1 b ? bit 7 ? rxcien: rx complete interrupt enable writing this bit to one enables interrupt on the rx cn flag. a usartn receive complete inter- rupt will be generated only if the rxcien bit is wr itten to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set . ? bit 6 ? txcien: tx complete interrupt enable writing this bit to one enables interrupt on the tx cn flag. a usartn transmit complete inter- rupt will be generated only if the txcien bit is wr itten to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set . ? bit 5 ? udrien: usartn data register empty interru pt enable writing this bit to one enables interrupt on the ud ren flag. a data register empty interrupt will be generated only if the udrien bit is written to o ne, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable writing this bit to one enables the usartn receiver . the receiver will override normal port operation for the rxdn pin when enabled. disabling the receiver will flush the receive buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable writing this bit to one enables the usartn transmit ter. the transmitter will override normal port operation for the txdn pin when enabled. the d isabling of the transmitter (writing txenn to zero) will not become effective until ongoing an d pending transmissions are completed, i.e., when the transmit shift register and transmit buffe r register do not contain data to be trans- mitted. when disabled, the transmitter will no long er override the txdn port. ? bit 2 ? ucszn2: character size the ucszn2 bits combined with the ucszn1:0 bit in u csrnc sets the number of data bits (character size) in a frame the receiver and transm itter use. ? bit 1 ? rxb8n: receive data bit 8 rxb8n is the ninth data bit of the received charact er when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 txb8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. must be written before writing the low bits to udrn. 17.11.7 usart0 control and status register c ? ucsr0 c bit 7 6 5 4 3 2 1 0 rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 ucsr1b read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 ucsr0c read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0
197 7682c?auto?04/08 at90can32/64/128 17.11.8 usart1 control and status register c ? ucsr1 c ? bit 7 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, these bit must be written to zero when ucsrnc is written. ? bit 6 ? umseln: usartn mode select this bit selects between asynchronous and synchrono us mode of operation. ? bit 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and check. if enabled, the transmitter will automatically generate and send the parity of the t ransmitted data bits within each frame. the receiver will generate a parity value for the incom ing data and compare it to the upmn0 setting. if a mismatch is detected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inse rted by the transmitter. the receiver ignores this setting. bit 7 6 5 4 3 2 1 0 ? umsel1 upm11 upm10 usbs1 ucsz11 ucsz10 ucpo1l ucsr1c read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 17-4. umseln bit settings umseln mode 0 asynchronous operation 1 synchronous operation table 17-5. upmn bits settings upmn1 upmn0 parity mode 0 0 disabled 0 1 reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 17-6. usbsn bit settings usbsn stop bit(s) 0 1-bit 1 2-bit
198 7682c?auto?04/08 at90can32/64/128 ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in u csrnb sets the number of data bits (character size) in a frame the receiver and transm itter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write t his bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sample, and the synchronous clock (xckn). 17.11.9 usart0 baud rate registers ? ubrr0l and ubrr 0h 17.11.10 usart1 baud rate registers ? ubrr1l and ubr r1h table 17-7. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 9-bit table 17-8. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xck edge falling xck edge 1 falling xck edge rising xck edge bit 15 14 13 12 11 10 9 8 ? ? ? ? ubrr0[11:8] ubrr0h ubrr0[7:0] ubrr0l 7 6 5 4 3 2 1 0 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 ? ? ? ? ubrr1[11:8] ubrr1h ubrr1[7:0] ubrr1l 7 6 5 4 3 2 1 0 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
199 7682c?auto?04/08 at90can32/64/128 ? bit 15:12 ? reserved bits these bits are reserved for future use. for compati bility with future devices, these bit must be written to zero when ubrrnh is written. ? bit 11:0 ? ubrrn11:0: usartn baud rate register this is a 12-bit register which contains the usartn baud rate. the ubrrnh contains the four most significant bits, and the ubrrnl contains the eight least significant bits of the usartn baud rate. ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. writing ubrrnl will trigger an imm ediate update of the baud rate prescaler. 17.12 examples of baud rate setting for standard crystal, resonator and external oscill ator frequencies, the most commonly used baud rates for asynchronous operation can be genera ted by using the ubrrn settings in table 17-9 up to table 17-12 . ubrrn values which yield an actual baud rate diff ering less than 0.5% from the target baud rate, are bold in the table. h igher error ratings are acceptable, but the receiver will have less noise resistance when the e rror ratings are high, especially for large serial frames (see ?asynchronous operational range? on page 191 ). the error values are calcu- lated using the following equation: note: 1. ubrrn = 0, error = 0.0% error[%] 1 baudrate closest match baudrate --------------------------------------------------- ----- ? ? ? ? ? 100% ? = table 17-9. examples of ubrrn settings for commonly frequencies baud rate (bps) f clk io = 1.0000 mhz f clk io = 1.8432 mhz f clk io = 2.0000 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error u brrn error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k ? ? ? ? ? ? 0 0.0% ? ? ? ? 250k ? ? ? ? ? ? ? ? ? ? ? ? 500k ? ? ? ? ? ? ? ? ? ? ? ? 1m ? ? ? ? ? ? ? ? ? ? ? ? max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kb ps
200 7682c?auto?04/08 at90can32/64/128 note: 1. ubrrn = 0, error = 0.0% table 17-10. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 3.6864 mhz f clk io = 4.0000 mhz f clk io = 7.3728 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error u brrn error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 500k ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ? ? ? ? ? ? ? ? ? ? 0 -7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 mbps 460.8 kbps 921. 6 kbps
201 7682c?auto?04/08 at90can32/64/128 note: 1. ubrrn = 0, error = 0.0% table 17-11. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 8.0000 mhz f clk io = 10.000 mhz f clk io = 11.0592 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error u brrn error 2400 207 0.2% 416 -0.1% 259 0.2% 520 0.0% 287 0.0% 575 0.0% 4800 103 0.2% 207 0.2% 129 0.2% 259 0.2% 143 0.0% 287 0.0% 9600 51 0.2% 103 0.2% 64 0.2% 129 0.2% 71 0.0% 143 0.0% 14.4k 34 -0.8% 68 0.6% 42 0.9% 86 0.2% 47 0.0% 95 0.0% 19.2k 25 0.2% 51 0.2% 32 -1.4% 64 0.2% 35 0.0% 71 0.0% 28.8k 16 2.1% 34 -0.8% 21 -1.4% 42 0.9% 23 0.0% 47 0.0% 38.4k 12 0.2% 25 0.2% 15 1.8% 32 -1.4% 17 0.0% 35 0.0% 57.6k 8 -3.5% 16 2.1% 10 -1.5% 21 -1.4% 11 0.0% 23 0.0% 76.8k 6 -7.0% 12 0.2% 7 1.9% 15 1.8% 8 0.0% 17 0.0% 115.2k 3 8.5% 8 -3.5% 4 9.6% 10 -1.5% 5 0.0% 11 0.0% 230.4k 1 8.5% 3 8.5% 2 -16.8% 4 9.6% 2 0.0% 5 0.0% 250k 1 0.0% 3 0.0% 2 -33.3% 4 0.0% 2 -7.8% 5 -7.8% 500k 0 0.0% 1 0.0% ? ? 2 -33.3% ? ? 2 -7.8% 1m ? ? 0 0.0% ? ? ? ? ? ? ? ? max. (1) 0.5 mbps 1 mbps 625 kbps 1.25 mbps 691.2 kbps 1.3824 mbp s
202 7682c?auto?04/08 at90can32/64/128 note: 1. ubrrn = 0, error = 0.0% table 17-12. examples of ubrrn settings for commonly frequencies (continued) baud rate (bps) f clk io = 12.0000 mhz f clk io = 14.7456 mhz f clk io = 16.0000 mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error u brrn error 2400 312 -0.2% 624 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 155 0.2% 312 -0.2% 191 0.0% 383 0.0% 207 0.2% 416 -0.1% 9600 77 0.2% 155 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 14.4k 51 0.2% 103 0.2% 63 0.0% 127 0.0% 68 0.6% 138 -0.1% 19.2k 38 0.2% 77 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 28.8k 25 0.2% 51 0.2% 31 0.0% 63 0.0% 34 -0.8% 68 0.6% 38.4k 19 -2.5% 38 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 57.6k 12 0.2% 25 0.2% 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 76.8k 9 -2.7% 19 -2.5% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 115.2k 6 -8.9% 12 0.2% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 230.4k 2 11.3% 6 -8.9% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 250k 2 0.0% 5 0.0% 3 -7.8% 6 5.3% 3 0.0% 7 0.0% 500k ? ? 2 0.0% 1 -7.8% 3 -7.8% 1 0.0% 3 0.0% 1m ? ? ? ? 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% max. (1) 750 kbps 1.5 mbps 921.6 kbps 1.8432 mbps 1 mbps 2 mbps
203 7682c?auto?04/08 at90can32/64/128 18. two-wire serial interface 18.1 features ? simple yet powerful and flexible communication inte rface, only two bus lines needed ? both master and slave operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slav e addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus l ines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in s leep mode 18.2 two-wire serial interface bus definition the two-wire serial interface (twi) is ideally suit ed for typical microcontroller applications. the twi protocol allows the systems designer to interco nnect up to 128 different devices using only two bi-directional bus lines, one for clock (scl) a nd one for data (sda). the only external hard- ware needed to implement the bus is a single pull-u p resistor for each of the twi bus lines. all devices connected to the bus have individual addres ses, and mechanisms for resolving bus contention are inherent in the twi protocol. figure 18-1. twi bus interconnection 18.2.1 twi terminology the following definitions are frequently encountere d in this section. device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc table 18-1. twi terminology term description master the device that initiates and terminates a transmis sion. the master also generates the scl clock slave the device addressed by a master transmitter the device placing data on the bus receiver the device reading data from the bus
204 7682c?auto?04/08 at90can32/64/128 18.2.2 electrical interconnection as depicted in figure 18-1 , both bus lines are connected to the positive supp ly voltage through pull-up resistors. the bus drivers of all twi-compl iant devices are open-drain or open-collector. this implements a wired-and function which is essen tial to the operation of the interface. a low level on a twi bus line is generated when one or mo re twi devices output a zero. a high level is output when all twi devices tri-state their outp uts, allowing the pull-up resistors to pull the lin e high. note that all avr devices connected to the tw i bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave address space. a detailed specification of the electrical char- acteristics of the twi is given in ?two-wire serial interface characteristics? on page 368 . two different sets of specifications are presented ther e, one relevant for bus speeds below 100 khz, and one valid for bus speeds up to 400 khz. 18.3 data transfer and frame format 18.3.1 transferring bits each data bit transferred on the twi bus is accompa nied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 18-2. data validity 18.3.2 start and stop conditions the master initiates and terminates a data transmis sion. the transmission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop conditio n, the bus is considered busy, and no other master should try to seize control of the bus . a special case occurs when a new start condition is issued between a start and stop condit ion. this is referred to as a repeated start condition, and is used when the master wishes to initiate a new transfer without relin- quishing control of the bus. after a repeated start , the bus is considered busy until the next stop. this is identical to the start behaviour, and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unless otherwise noted. as depicted below, start and stop conditions are signa lled by changing the level of the sda line when the scl line is high. sda scl data stable data stable data change
205 7682c?auto?04/08 at90can32/64/128 figure 18-3. start, repeated start and stop conditions 18.3.3 address packet format all address packets transmitted on the twi bus are 9 bits long, consisting of 7 address bits, one read/write control bit and an acknowledge bit. if t he read/write bit is set, a read opera- tion is to be performed, otherwise a write operatio n should be performed. when a slave recognizes that it is being addressed, it should ac knowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the mas- ter?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeated start cond ition to initiate a new transmission. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. s lave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should re spond by pulling the sda line low in the ack cycle. a general call is used when a master wishes to transmit the same message to several slaves in the system. when the general call address followed by a write bit is transmitted on the bus, all slaves set up to acknowledge the general c all will pull the sda line low in the ack cycle. the following data packets will then be received by all the slaves that acknowledged the general call. note that transmitting the general call addre ss followed by a read bit is meaningless, as this would cause contention if several slaves start ed transmitting different data. all addresses of the format 1111 xxx should be rese rved for future purposes. figure 18-4. address packet format 18.3.4 data packet format all data packets transmitted on the twi bus are 9 b its long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the receiver is responsible for acknowledging the reception. an sda scl start stop repeated start stop start sda scl start 1 2 7 8 9 addr msb addr lsb r/w ack
206 7682c?auto?04/08 at90can32/64/128 acknowledge (ack) is signalled by the receiver pull ing the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason cannot r eceive any more bytes, it should inform the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. figure 18-5. data packet format 18.3.5 combining address and data packets into a tra nsmission a transmission basically consists of a start condit ion, a sla+r/w, one or more data packets and a stop condition. an empty message, consisting of a start followed by a stop condi- tion, is illegal. note that the wired-anding of the scl line can be used to implement handshaking between the master and the slave. the s lave can extend the scl low period by pulling the scl line low. this is useful if the clo ck speed set up by the master is too fast for the slave, or the slave needs extra time for processing between the data transmissions. the slave extending the scl low period will not affect the sc l high period, which is determined by the master. as a consequence, the slave can reduce the twi data transfer speed by prolonging the scl duty cycle. figure 18-6 shows a typical data transmission. note that sever al data bytes can be transmitted between the sla+r/w and the stop condition, dependi ng on the software protocol imple- mented by the application software. figure 18-6. typical data transmission 18.4 multi-master bus systems, arbitration and synch ronization the twi protocol allows bus systems with several ma sters. special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. two problems arise in multi-master systems: 1 2 7 8 9 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop , repeated start or next data byte 1 2 7 8 9 data byte data msb data lsb ack sda scl start 1 2 7 8 9 addr msb addr lsb r/w ack sla+r/w stop
207 7682c?auto?04/08 at90can32/64/128 ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transm ission when they discover that they have lost the selection process. this selection process is called arbitration. when a contending master discovers that it has lost the arbitration p rocess, it should immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e., the data being transferred on the bus must no t be corrupted. ? different masters may use different scl frequencie s. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will facilitate the arbitrat ion process. the wired-anding of the bus lines is used to solve both these problems. the serial clocks from all masters will be wired-anded, yielding a combine d clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low p eriod. note that all masters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 18-7. scl synchronization between multiple masters arbitration is carried out by all masters continuou sly monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only l ose arbitration when it outputs a high sda value while another master outputs a low value. the losin g master should immediately go to slave mode, checking if it is being addressed by the winn ing master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will continue until onl y one master remains, and this may take many bits. if several masters are trying to address the same slave, arbitration will continue into the data packet. ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start counting low period masters start counting high perio
208 7682c?auto?04/08 at90can32/64/128 figure 18-8. arbitration between two masters note that arbitration is not allowed between: ? a repeated start condition and a data bit ? a stop condition and a data bit ? a repeated start and a stop condition it is the user software?s responsibility to ensure that these illegal arbitration conditions never occur. this implies that in multi-master systems, a ll data transfers must use the same composi- tion of sla+r/w and data packets. in other words: a ll transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 18.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 18-9 . all registers drawn in a thick line are accessible through the av r data bus. sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda
209 7682c?auto?04/08 at90can32/64/128 figure 18-9. overview of the twi module 18.5.1 scl and sda pins these pins interface the avr twi with the rest of t he mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi sp ecification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns . note that the internal pullups in the avr pads can be enabled by setting the port bits corres ponding to the scl and sda pins, as explained in the i/o port section. the internal pul l-ups can in some systems eliminate the need for external ones. 18.5.2 bit rate generator unit this unit controls the period of scl when operating in a master mode. the scl period is con- trolled by settings in the twi bit rate register (t wbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at least 1 6 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: ? twbr = value of the twi bit rate register ? twps = value of the prescaler bits in the twi stat us register note: twbr should be 10 or higher if the twi operate s in master mode. if twbr is lower than 10, the master may produce an incorrect output on sda and s cl for the reminder of the byte. the prob- lem occurs when operating the twi in master mode, s ending start + sla + r/w to a slave (a slave does not need to be connected to the bus for the condition to happen). twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) scl frequency clkio 16 2(twbr) 4 twps ? + ??????????????????????????????????????????????????? ???????? =
210 7682c?auto?04/08 at90can32/64/128 18.5.3 bus interface unit this unit contains the data and address shift regis ter (twdr), a start/stop controller and arbitration detection hardware. the twdr contains t he address or data bytes to be transmitted, or the address or data bytes received. in addition to the 8-bit twdr, the bus interface unit also contains a register containing the (n)ack bit to be transmitted or received. this (n)ack regis- ter is not directly accessible by the application s oftware. however, when receiving, it can be set or cleared by manipulating the twi control register (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for genera tion and detection of start, repeated start, and stop conditions. the start/stop controll er is able to detect start and stop conditions even when the avr mcu is in one of the s leep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as master, the arbitration detection hardware continu- ously monitors the transmission trying to determine if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. corre ct action can then be taken and appropriate status codes generated. 18.5.4 address match unit the address match unit checks if received address b ytes match the 7-bit address in the twi address register (twar). if the twi general call re cognition enable (twgce) bit in the twar is written to one, all incoming address bits w ill also be compared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge its addre ss, depending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addressed by a master. if another interrupt (e.g., int0) occurs during twi power-down address match and wake s up the cpu, the twi aborts opera- tion and return to it?s idle state. if this cause a ny problems, ensure that twi address match is the only enabled interrupt when entering power-down. 18.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when an event requirin g the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is a sserted. in the next clock cycle, the twi sta- tus register (twsr) is updated with a status code i dentifying the event. the twsr only contains relevant status information when the twi i nterrupt flag is asserted. at all other times, the twsr contains a special status code indicating that no relevant status information is avail- able. as long as the twint flag is set, the scl lin e is held low. this allows the application software to complete its tasks before allowing the twi transmission to continue. the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated sta rt condition ? after the twi has transmitted sla+r/w ? after the twi has transmitted an address byte ? after the twi has lost arbitration ? after the twi has been addressed by own slave addr ess or general call ? after the twi has received a data byte ? after a stop or repeated start has been received w hile still addressed as a slave
211 7682c?auto?04/08 at90can32/64/128 ? when a bus error has occurred due to an illegal st art or stop condition 18.6 twi register description 18.6.1 twi bit rate register ? twbr ? bits 7.0 ? twi bit rate register twbr selects the division factor for the bit rate g enerator. the bit rate generator is a frequency divider which generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 209 for calculating bit rates. 18.6.2 twi control register ? twcr the twcr is used to control the operation of the tw i. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control haltin g of the bus while the data to be written to the bus are written to the twdr. it also indicates a wr ite collision if data is attempted written to twdr while the register is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finish ed its current job and expects application software response. if the i-bit in sreg and twie in twcr are set, the mcu will jump to the twi interrupt vector. while the twint flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automati- cally cleared by hardware when executing the interr upt routine. also note that clearing this flag starts the operation of the twi, so all accesses to the twi address register (twar), twi sta- tus register (twsr), and twi data register (twdr) m ust be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the ack pul se. if the twea bit is written to one, the ack pulse is generated on the twi bus if the follow ing conditions are met: 1. the device?s own slave address has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the two-wire serial bus temporarily. address recognition can the n be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit bit 7 6 5 4 3 2 1 0 twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value 0 0 0 0 0 0 0 0
212 7682c?auto?04/08 at90can32/64/128 the application writes the twsta bit to one when it desires to become a master on the two- wire serial bus. the twi hardware checks if the bus is available, and generates a start con- dition on the bus if it is free. however, if the bu s is not free, the twi waits until a stop condition is detected, and then generates a new start conditi on to claim the bus master status. twsta must be cleared by software when the start conditio n has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode will ge nerate a stop condition on the two-wire serial bus. when the stop condition is executed on the bus, the twsto bit is cleared auto- matically. in slave mode, setting the twsto bit can be used to recover from an error condition. this will not generate a stop condition, but the tw i returns to a well-defined unaddressed slave mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleared by writing the twdr regis ter when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activates th e twi interface. when twen is written to one, the twi takes control over the i/o pins connec ted to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit i s written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ong oing operation. ? bit 1 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, this must be written to zero when twcr is written. ? bit 0 ? twie: twi interrupt enable when this bit is written to one, and the i-bit in s reg is set, the twi interrupt request will be acti- vated for as long as the twint flag is high. 18.6.3 twi status register ? twsr ? bits 7.3 ? tws: twi status these 5 bits reflect the status of the twi logic an d the two-wire serial bus. the different status codes are described later in this section. note tha t the value read from twsr contains both the 5-bit status value and the 2-bit prescaler value. t he application designer should mask the pres- caler bits to zero when checking the status bits. t his makes status checking independent of prescaler setting. this approach is used in this da tasheet, unless otherwise noted. ? bit 2 ? res: reserved bit this bit is reserved and will always read as zero. bit 7 6 5 4 3 2 1 0 tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write r r r r r r r/w r/w initial value 1 1 1 1 1 0 0 0
213 7682c?auto?04/08 at90can32/64/128 ? bits 1.0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 209 . the value of twps1.0 is used in the equation. 18.6.4 twi data register ? twdr in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writable whi le the twi is not in the process of shifting a byte . this occurs when the twi interrupt flag (twint) is set by hardware. note that the data register cannot be initialized by the user before the first interrupt occurs. the data in twdr remains sta- ble as long as twint is set. while data is shifted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on t he bus, except after a wake up from a sleep mode by the twi interrupt. in this case, the conten ts of twdr is undefined. in the case of a lost bus arbitration, no data is lost in the transition from master to slave. handling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. ? bits 7.0 ? twd: twi data register these eight bits constitute the next data byte to b e transmitted, or the latest data byte received on the twi serial bus. 18.6.5 twi (slave) address register ? twar ? bits 7.1 ? twa: twi (slave) address register these seven bits constitute the slave address of th e twi unit. the twar should be loaded with the 7-bit slave address to which the twi will respo nd when programmed as a slave transmitter or receiver, and not needed in the master modes. in multimaster systems, twar must be set in masters which can be addressed as slaves by other m asters. ? bit 0 ? twgce: twi general call recognition enable bit table 18-2. twi bit rate prescaler twps1 twps0 prescaler value 0 0 1 0 1 4 1 0 16 1 1 64 bit 7 6 5 4 3 2 1 0 twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 bit 7 6 5 4 3 2 1 0 twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 0
214 7682c?auto?04/08 at90can32/64/128 twgce is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an in terrupt request is generated. if set, this bit enables the recognition of a general call given ove r the twi serial bus. 18.7 using the twi the avr twi is byte-oriented and interrupt based. i nterrupts are issued after all bus events, like reception of a byte or transmission of a start cond ition. because the twi is interrupt-based, the application software is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr togethe r with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should gener- ate an interrupt request. if the twie bit is cleare d, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finish ed an operation and awaits application response. in this case, the twi status register (tw sr) contains a value indicating the current state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 18-10 is a simple example of how the application can int erface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this description is quite abstract, a more detailed explanation follows later in this section. a simple code example imple- menting the desired behavior is also presented. figure 18-10. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transm it a start condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a on e to twint clears the flag. the twi will not start any operation as long as the twint b it in twcr is set. immediately after start sla+w a data a stop 1. application writes to twcr to initiate transmission of start. 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sendt, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one. 7. check twsr to see if d was sent and ack received application loads appropr control signals to send s into twcr, making sure th twint is written to one. twi bus indicate twint set application action twi hardware action
215 7682c?auto?04/08 at90can32/64/128 the application has cleared twint, the twi will ini tiate transmission of the start condition. 2. when the start condition has been transmitted, th e twint flag in twcr is set, and twsr is updated with a status code indicating that the start condition has success- fully been sent. 3. the application software should now examine the v alue of twsr, to make sure that the start condition was successfully transmitted. i f twsr indicates otherwise, the application software might take some special action , like calling an error routine. assuming that the status code is as expected, the a pplication must load sla+w into twdr. remember that twdr is used both for address a nd data. after twdr has been loaded with the desired sla+w, a specific valu e must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is importa nt that the twint bit is set in the value written. writing a one to twint clears the flag. th e twi will not start any operation as long as the twint bit in twcr is set. immediately a fter the application has cleared twint, the twi will initiate transmission of the ad dress packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the address packet has success- fully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 5. the application software should now examine the v alue of twsr, to make sure that the address packet was successfully transmitted, an d that the value of the ack bit was as expected. if twsr indicates otherwise, the appli cation software might take some special action, like calling an error routine. assu ming that the status code is as expected, the application must load a data packet i nto twdr. subsequently, a specific value must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write is des cribed later on. however, it is important that the twint bit is set in the value wr itten. writing a one to twint clears the flag. the twi will not start any operation as l ong as the twint bit in twcr is set. immediately after the application has cleared twint , the twi will initiate transmission of the data packet. 6. when the data packet has been transmitted, the tw int flag in twcr is set, and twsr is updated with a status code indicating that the data packet has successfully been sent. the status code will also reflect whethe r a slave acknowledged the packet or not. 7. the application software should now examine the v alue of twsr, to make sure that the data packet was successfully transmitted, and t hat the value of the ack bit was as expected. if twsr indicates otherwise, the applicat ion software might take some spe- cial action, like calling an error routine. assumin g that the status code is as expected, the application must write a specific value to twcr , instructing the twi hardware to transmit a stop condition. which value to write is described later on. however, it is important that the twint bit is set in the value wr itten. writing a one to twint clears the flag. the twi will not start any operation as l ong as the twint bit in twcr is set. immediately after the application has cleared twint , the twi will initiate transmission of the stop condition. note that twint is not set a fter a stop condition has been sent. even though this example is simple, it shows the pr inciples involved in all twi transmissions. these can be summarized as follows: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pulled low until twint is clea red.
216 7682c?auto?04/08 at90can32/64/128 ? when the twint flag is set, the user must update a ll twi registers with the value relevant for the next twi bus cycle. as an example, twdr mus t be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending a pplication software tasks have been completed, twcr is written. when writing twcr, the twint bit should be set. writing a one to twint clears the flag. the twi will then com mence executing whatever operation was specified by the twcr setting. in the following an assembly and c implementation o f the example is given. note that the code below assumes that several definitions have been ma de for example by using include-files. assembly code example c example comments 1 ldi r16, (1< 217 7682c?auto?04/08 at90can32/64/128 18.8 transmission modes the twi can operate in one of four major modes. the se are named master transmitter (mt), master receiver (mr), slave transmitter (st) and sl ave receiver (sr). several of these modes can be used in the same application. as an ex ample, the twi can use mt mode to write data into a twi eeprom, mr mode to read the data ba ck from the eeprom. if other masters are present in the system, some of these might tran smit data to the twi, and then sr mode would be used. it is the application software that decides which modes are legal. the following sections describe each of these modes . possible status codes are described along with figures detailing data transmission in e ach of the modes. these figures contain the following abbreviations: s : start condition rs : repeated start condition r : read bit (high level at sda) w : write bit (low level at sda) a : acknowledge bit (low level at sda) a : not acknowledge bit (high level at sda) data : 8-bit data byte p : stop condition sla : slave address in figure 18-12 to figure 18-18 , circles are used to indicate that the twint flag is set. the num- bers in the circles show the status code held in tw sr, with the prescaler bits masked to zero. at these points, actions must be taken by the applicat ion to continue or complete the twi transfer. the twi transfer is suspended until the twint flag is cleared by software. when the twint flag is set, the status code in twsr is used to determine the appropriate soft- ware action. for each status code, the required sof tware action and details of the following serial transfer are given in table 18-3 to table 18-6 . note that the prescaler bits are masked to zero i n these tables. 18.8.1 master transmitter mode in the master transmitter mode, a number of data by tes are transmitted to a slave receiver (see figure 18-11 ). in order to enter a master mode, a start conditi on must be transmitted. the for- mat of the following address packet determines whet her master transmitter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero.
218 7682c?auto?04/08 at90can32/64/128 figure 18-11. data transfer in master transmitter mode a start condition is sent by writing the following value to twcr: twen must be set to enable the two-wire serial inte rface, twsta must be written to one to transmit a start condition and twint must be writte n to one to clear the twint flag. the twi will then test the two-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been tran smitted, the twint flag is set by hard- ware, and the status code in twsr will be 0x08 (see table 18-3 ). in order to enter mt mode, sla+w must be transmitted. this is done by writing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to continu e the transfer. this is accomplished by writing the following value to twcr: when sla+w have been transmitted and an acknowledgm ent bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate actio n to be taken for each of these status codes is detailed in table 18-3 . when sla+w has been successfully transmitted, a dat a packet should be transmitted. this is done by writing the data byte to twdr. twdr must on ly be written when twint is high. if not, the access will be discarded, and the write collisi on bit (twwc) will be set in the twcr regis- ter. after updating twdr, the twint bit should be c leared (by writing it to one) to continue the transfer. this is accomplished by writing the follo wing value to twcr: this scheme is repeated until the last byte has bee n sent and the transfer is ended by generat- ing a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x 1 0 x 1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 0 x 1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 0 x 1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 1 x 1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x 1 0 x 1 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master transmitter slave receiver
219 7682c?auto?04/08 at90can32/64/128 after a repeated start condition (state 0x10) the t wo-wire serial interface can access the same slave again, or a new slave without transmitti ng a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. table 18-3. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w x 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r x x 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack wi ll be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will b e transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack wi ll be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will b e transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack wi ll be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will b e transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack wi ll be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will b e transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not addres sed slave mode entered a start condition will be transmitted when the bus be- comes free
220 7682c?auto?04/08 at90can32/64/128 figure 18-12. formats and states in the master transmitter mode s sla w a data a p 0x08 0x18 0x28 r sla w 0x10 a p 0x20 p 0x30 a or a 0x38 a other master continues a or a 0x38 other master continues r a 0x68 other master continues 0x78 0xb0 t o corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero s
221 7682c?auto?04/08 at90can32/64/128 18.8.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 18-13 ). in order to enter a master mode, a start conditi on must be transmitted. the for- mat of the following address packet determines whet her master transmitter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 18-13. data transfer in master receiver mode a start condition is sent by writing the following value to twcr: twen must be written to one to enable the two-wire serial interface, twsta must be written to one to transmit a start condition and twint must be set to clear the twint flag. the twi will then test the two-wire serial bus and generate a st art condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 18-3 ). in order to enter mr mode, sla+r must be transmitted. this is done by writing sla+r to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the tran sfer. this is accomplished by writing the follow- ing value to twcr: when sla+r have been transmitted and an acknowledgm ent bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate actio n to be taken for each of these status codes is detailed in table 18-12 . received data can be read from the twdr register when the twint flag is set high by hardware. this scheme is repeat ed until the last byte has been received. after the last byte has been received, the mr should info rm the st by sending a nack after the last received data byte. the transfer is ended by genera ting a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x 1 0 x 1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 0 x 1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x 0 1 x 1 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver
222 7682c?auto?04/08 at90can32/64/128 a repeated start condition is generated by writing the following value to twcr: after a repeated start condition (state 0x10) the t wo-wire serial interface can access the same slave again, or a new slave without transmitti ng a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. figure 18-14. formats and states in the master receiver mode twcr twint twea twsta twsto twwc twen ? twie value 1 x 1 0 x 1 0 x s sla r a data a 0x08 0x40 0x50 sla r 0x10 a p 0x48 a or a 0x38 other master continues 0x38 other master continues w a 0x68 other master continues 0x78 0xb0 t o corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p data a 0x58 a r s
223 7682c?auto?04/08 at90can32/64/128 18.8.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 18-15 ). all the status codes mentioned in this section a ssume that the prescaler bits are zero or are masked to zero. figure 18-15. data transfer in slave receiver mode table 18-4. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r x 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w x x 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not addres sed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag w ill be reset stop condition followed by a start condition will b e transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag w ill be reset stop condition followed by a start condition will b e transmitted and twsto flag will be reset device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver
224 7682c?auto?04/08 at90can32/64/128 to initiate the slave receiver mode, twar and twcr must be initialized as follows: the upper seven bits are the address to which the t wo-wire serial interface will respond when addressed by a master. if the lsb is set, the twi w ill respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the device?s own slave addres s or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi w aits until it is addressed by its own slave address (or the general call address if enabl ed) followed by the data direction bit. if the direction bit is ?0? (write), the twi will operate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been r eceived, the twint flag is set and a valid status code can be read from twsr. the status code is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 18-5 . the slave receiver mode may also be entered if arbi tration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the twi will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the two-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies th at the twea bit may be used to temporarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave address or the general call address by using the two-wire serial bus clock as a clock sour ce. the part will then wake up from sleep and the twi will hold the scl clock low during the wake up and until the twint flag is cleared (by writing it to one). further data reception will be carried out as normal, with the avr clocks running as normal. observe that if the avr is set u p with a long start-up time, the scl line may be held low for a long time, blocking other data tr ansmissions. note that the two-wire serial interface data regist er ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 1 0 0 0 1 0 x
225 7682c?auto?04/08 at90can32/64/128 table 18-5. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as mas- ter; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as mas- ter; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free
226 7682c?auto?04/08 at90can32/64/128 figure 18-16. formats and states in the slave receiver mode s sla w a data a 0x60 0x80 0x88 a 0x68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data a 0x80 0xa0 p or s a a data a 0x70 0x90 0x98 a 0x78 p or s data a 0x90 0xa0 p or s a general call arbitration lost as master and addressed as slave by general call data a
227 7682c?auto?04/08 at90can32/64/128 18.8.4 slave transmitter mode in the slave transmitter mode, a number of data byt es are transmitted to a master receiver (see figure 18-17 ). all the status codes mentioned in this section a ssume that the prescaler bits are zero or are masked to zero. figure 18-17. data transfer in slave transmitter mode to initiate the slave transmitter mode, twar and tw cr must be initialized as follows: the upper seven bits are the address to which the t wo-wire serial interface will respond when addressed by a master. if the lsb is set, the twi w ill respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the device?s own slave addres s or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi w aits until it is addressed by its own slave address (or the general call address if enabl ed) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate i n st mode, otherwise sr mode is entered. after its own slave address and the write bit have been r eceived, the twint flag is set and a valid status code can be read from twsr. the status code is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 18-6 . the slave transmitter mode may also be entered if a rbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfe r, the twi will transmit the last byte of the trans - fer. state 0xc0 or state 0xc8 will be entered, depe nding on whether the master receiver transmits a nack or ack after the final byte. the t wi is switched to the not addressed slave mode, and will ignore the master if it continues th e transfer. thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if th e master demands additional data bytes (by transmitting ack), even though the slave has transm itted the last byte (twea zero and expect- ing nack from the master). twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 1 0 0 0 1 0 x device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master slave transmitter receiver
228 7682c?auto?04/08 at90can32/64/128 while twea is zero, the twi does not respond to its own slave address. however, the two-wire serial bus is still monitored and address recogniti on may resume at any time by setting twea. this implies that the twea bit may be used to tempo rarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave address or the general call address by using the two-wire serial bus clock as a clock sour ce. the part will then wake up from sleep and the twi will hold the scl clock will low during the wake up and until the twint flag is cleared (by writing it to one). further data transm ission will be carried out as normal, with the avr clocks running as normal. observe that if the a vr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the two-wire serial interface data regist er ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. table 18-6. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack shou ld be received data byte will be transmitted and ack should be rec eived 0xb0 arbitration lost in sla+r/w as mas- ter; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack shou ld be received data byte will be transmitted and ack should be rec eived 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack shou ld be received data byte will be transmitted and ack should be rec eived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free
229 7682c?auto?04/08 at90can32/64/128 figure 18-18. formats and states in the slave transmitter mode 18.8.5 miscellaneous states there are two status codes that do not correspond t o a defined twi state, see table 18-7 . status 0xf8 indicates that no relevant information is available because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a two-wire serial bus transfer. a bus error occurs when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the s erial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twi nt is set. to recover from a bus error, the twsto flag must set and twint must be cleared by wr iting a logic one to it. this causes the twi to enter the not addressed slave mode and to cl ear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. s sla r a data a 0xa8 0xb8 a 0xb0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data 0xc0 data a a 0xc8 p or s all 1's a table 18-7. miscellaneous states status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is aff ected, no stop condition is sent on the bus. in all cases, the bus is releas ed and twsto is cleared.
230 7682c?auto?04/08 at90can32/64/128 18.8.6 combining several twi modes in some cases, several twi modes must be combined i n order to complete the desired action. consider for example reading data from a serial eep rom. typically, such a transfer involves the following steps: 1. the transfer must be initiated 2. the eeprom must be instructed what location shoul d be read 3. the reading must be performed 4. the transfer must be finished note that data is transmitted both from master to s lave and vice versa. the master must instruct the slave what location it wants to read, requiring the use of the mt mode. subsequently, data must be read from the slave, implying the use of th e mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this principle is violated in a multimaster sys- tem, another master can alter the data pointer in t he eeprom between steps 2 and 3, and the master will read the wrong data location. such a ch ange in transfer direction is accomplished by transmitting a repeated start between the transmiss ion of the address byte and reception of the data. after a repeated start, the master kee ps ownership of the bus. the following figure shows the flow in this transfer. figure 18-19. combining several twi modes to access a serial eepr om master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p
231 7682c?auto?04/08 at90can32/64/128 18.9 multi-master systems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simulta- neously by one or more of them. the twi standard en sures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. an example of an arbit ration situation is depicted below, where two masters are trying to transmit data to a slave rece iver. figure 18-20. an arbitration example several different scenarios may arise during arbitr ation, as described below: ? two or more masters are performing identical commu nication with the same slave. in this case, neither the slave nor any of the masters will know about the bus contention. ? two or more masters are accessing the same slave w ith different data or direction bit. in this case, arbitration will occur, either in the read/wr ite bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing masters will switch to not addressed slave m ode or wait until the bus is free and transmit a new start condition, depending on applic ation software action. ? two or more masters are accessing different slaves . in this case, arbitration will occur in the sla bits. masters trying to output a one on sda whi le another master outputs a zero will lose the arbitration. masters losing arbitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed , they will switch to sr or st mode, depending on the value of the read/write bit. if th ey are not being addressed, they will switch to not addressed slave mode or wait until th e bus is free and transmit a new start condition, depending on application software action . device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc master transmitter slave receiver slave receiver
232 7682c?auto?04/08 at90can32/64/128 this is summarized in figure 18-21 . possible status values are given in circles. figure 18-21. possible status codes caused by arbitration own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction yes write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read 0xb0 0x68 / 0x78 0x38 sla start data stop
233 7682c?auto?04/08 at90can32/64/128 19. controller area network - can the controller area network (can) protocol is a rea l-time, serial, broadcast protocol with a very high level of security. the at90can32/64/128 can co ntroller is fully compatible with the can specification 2.0 part a and part b. it delivers th e features required to implement the kernel of the can bus protocol according to the iso/osi refer ence model: ? the data link layer - the logical link control (llc) sublayer - the medium access control (mac) sublayer ? the physical layer - the physical signalling (pls) sublayer - not supported - the physical medium attach (pma) - not supported - the medium dependent interface (m di) the can controller is able to handle all types of f rames (data, remote, error and overload) and achieves a bitrate of 1 mbit/s. 19.1 features ? full can controller ? fully compliant with can standard rev 2.0 a and re v 2.0 b ? 15 mob (message object) with their own: ? 11 bits of identifier tag (rev 2.0 a), 29 bits of identifier tag (rev 2.0 b) ? 11 bits of identifier mask (rev 2.0 a), 29 bits of identifier mask (rev 2.0 b) ? 8 bytes data buffer (static allocation) ? tx, rx, frame buffer or automatic reply configurat ion ? time stamping ? 1 mbit/s maximum transfer rate at 8 mhz ? ttc timer ? listening mode (for spying or autobaud) 19.2 can protocol the can protocol is an international standard defin ed in the iso 11898 for high speed and iso 11519-2 for low speed. 19.2.1 principles can is based on a broadcast communication mechanism . this broadcast communication is achieved by using a message oriented transmission p rotocol. these messages are identified by using a message identifier. such a message identifi er has to be unique within the whole network and it defines not only the content but also the pr iority of the message. the priority at which a message is transmitted comp ared to another less urgent message is specified by the identifier of each message. the pr iorities are laid down during system design in the form of corresponding binary values and cannot be changed dynamically. the identifier with the lowest binary number has the highest priority. bus access conflicts are resolved by bit-wise arbit ration on the identifiers involved by each node observing the bus level bit for bit. this happens i n accordance with the "wired and" mechanism,
234 7682c?auto?04/08 at90can32/64/128 by which the dominant state overwrites the recessiv e state. the competition for bus allocation is lost by all nodes with recessive transmission and d ominant observation. all the "losers" automat- ically become receivers of the message with the hig hest priority and do not re-attempt transmission until the bus is available again. 19.2.2 message formats the can protocol supports two message frame formats , the only essential difference being in the length of the identifier. the can standard fram e, also known as can 2.0 a, supports a length of 11 bits for the identifier, and the can e xtended frame, also known as can 2.0 b, sup- ports a length of 29 bits for the identifier. 19.2.2.1 can standard frame figure 19-1. can standard frames a message in the can standard frame format begins w ith the "start of frame (sof)", this is fol- lowed by the "arbitration field" which consist of t he identifier and the "remote transmission request (rtr)" bit used to distinguish between the data frame and the data request frame called remote frame. the following "control field" contains the "identifier extension (ide)" bit and the "data length code (dlc)" used to indicate t he number of following data bytes in the "data field". in a remote frame, the dlc contains t he number of requested data bytes. the "data field" that follows can hold up to 8 data bytes. th e frame integrity is guaranteed by the following "cyclic redundant check (crc)" sum. the "acknowledg e (ack) field" compromises the ack slot and the ack delimiter. the bit in the ack slot is sent as a recessive bit and is overwritten as a dominant bit by the receivers which have at this time received the data correctly. correct mes- sages are acknowledged by the receivers regardless of the result of the acceptance test. the end of the message is indicated by "end of frame (e of)". the "intermission frame space (ifs)" is the minimum number of bits separating con secutive messages. if there is no following bus access by any node, the bus remains idle. 11-bit identifier id10..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc 0 - 8 bytes sof sof rtr ide r0 ack 7 bits intermission 3 bits bus idle bus idle (indefinite arbitration field data field data frame control field end of frame crc field ack field interframe space 11-bit identifier id10..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc sof sof rtr ide r0 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) arbitration field remote frame control field end of frame crc field ack field interframe space
235 7682c?auto?04/08 at90can32/64/128 19.2.2.2 can extended frame figure 19-2. can extended frames a message in the can extended frame format is likel y the same as a message in can standard frame format. the difference is the length of the i dentifier used. the identifier is made up of the existing 11-bit identifier (base identifier) and an 18-bit extension (identifier extension). the dis- tinction between can standard frame format and can extended frame format is made by using the ide bit which is transmitted as dominant in cas e of a frame in can standard frame format, and transmitted as recessive in the other case. 19.2.2.3 format co-existence as the two formats have to co-exist on one bus, it is laid down which message has higher priority on the bus in the case of bus access collision with different formats and the same identifier / base identifier: the message in can standard frame format always has priority over the mes- sage in extended format. there are three different types of can modules avai lable: ? 2.0a - considers 29 bit id as an error ? 2.0b passive - ignores 29 bit id messages ? 2.0b active - handles both 11 and 29 bit id messag es 19.2.3 can bit timing to ensure correct sampling up to the last bit, a ca n node needs to re-synchronize throughout the entire frame. this is done at the beginning of each message with the falling edge sof and on each recessive to dominant edge. 19.2.3.1 bit construction one can bit time is specified as four non-overlappi ng time segments. each segment is con- structed from an integer multiple of the time quant um. the time quantum or tq is the smallest discrete timing resolution used by a can node. 11-bit base identifier idt28..18 interframe space crc del. ack del. 15-bit crc 0 - 8 bytes sof sof srr ide ack 7 bits intermission 3 bits bus idle bus idle (indefini arbitration field arbitration field data field data frame control field control field end of frame crc field ack field interframe space 11-bit base identifier idt28..18 18-bit identifier extension id17..0 18-bit identifier extension id17..0 interframe space 4-bit dlc dlc4..0 crc del. ack del. 15-bit crc sof sof srr ide r0 4-bit dlc dlc4..0 rtr rtr r0 r1 r1 ack 7 bits intermission 3 bits bus idle bus idle (indefinite) remote frame end of frame crc field ack field interframe space
236 7682c?auto?04/08 at90can32/64/128 figure 19-3. can bit construction 19.2.3.2 synchronization segment the first segment is used to synchronize the variou s bus nodes. on transmission, at the start of this segment, the current bit level is output. if there is a bit stat e change between the previous bit and the current bit , then the bus state change is expected to occur within this segment by the receiving nodes. 19.2.3.3 propagation time segment this segment is used to compensate for signal delay s across the network. this is necessary to compensate for signal propagat ion delays on the bus line and through the transceivers of the bus nodes. 19.2.3.4 phase segment 1 phase segment 1 is used to compensate for edge phas e errors. this segment may be lengthened during re-synchroniz ation. 19.2.3.5 sample point the sample point is the point of time at which the bus level is read and interpreted as the value of the respective bit. its location is at the end o f phase segment 1 (between the two phase segments). 19.2.3.6 phase segment 2 this segment is also used to compensate for edge ph ase errors. this segment may be shortened during re-synchroniza tion, but the length has to be at least as long as the information processing time (ipt) and m ay not be more than the length of phase segment 1. 19.2.3.7 information processing time it is the time required for the logic to determine the bit level of a sampled bit. time quantum (producer) nominal can bit time segments (producer) sync_seg prop_seg phase_seg_1 phase_seg_2 propagation delay segments (consumer) sync_seg prop_seg phase_seg_1 phase_seg_2 sample point transmission point (producer) can frame (producer)
237 7682c?auto?04/08 at90can32/64/128 the ipt begins at the sample point, is measured in tq and is fixed at 2tq for the atmel can. since phase segment 2 also begins at the sample poi nt and is the last segment in the bit time, ps2 minimum shall not be less than the ipt. 19.2.3.8 bit lengthening as a result of resynchronization, phase segment 1 m ay be lengthened or phase segment 2 may be shortened to compensate for oscillator toler ances. if, for example, the transmitter oscilla- tor is slower than the receiver oscillator, the nex t falling edge used for resynchronization may be delayed. so phase segment 1 is lengthened in order to adjust the sample point and the end of the bit time. 19.2.3.9 bit shortening if, on the other hand, the transmitter oscillator i s faster than the receiver one, the next falling edge used for resynchronization may be too early. s o phase segment 2 in bit n is shortened in order to adjust the sample point for bit n+1 and th e end of the bit time 19.2.3.10 synchronization jump width the limit to the amount of lengthening or shortenin g of the phase segments is set by the resyn- chronization jump width. this segment may not be longer than phase segment 2 . 19.2.3.11 programming the sample point programming of the sample point allows "tuning" of the characteristics to suit the bus. early sampling allows more time quanta in the phase segment 2 so the synchronization jump width can be programmed to its maximum. this maximu m capacity to shorten or lengthen the bit time decreases the sensitivity to node oscillat or tolerances, so that lower cost oscillators such as ceramic resonators may be used. late sampling allows more time quanta in the propag ation time segment which allows a poorer bus topology and maximum bus length. 19.2.3.12 synchronization hard synchronization occurs on the recessive-to-dom inant transition of the start bit. the bit time is restarted from that edge. re-synchronization occurs when a recessive-to-domin ant edge doesn't occur within the syn- chronization segment in a message. 19.2.4 arbitration the can protocol handles bus accesses according to the concept called ?carrier sense multiple access with arbitration on message priority?. during transmission, arbitration on the can bus can be lost to a competing device with a higher priority can identifier. this arbitration concept a voids collisions of messages whose transmis- sion was started by more than one node simultaneous ly and makes sure the most important message is sent first without time loss. the bus access conflict is resolved during the arbi tration field mostly over the identifier value. if a data frame and a remote frame with the same identif ier are initiated at the same time, the data frame prevails over the remote frame (c.f. rtr bit) .
238 7682c?auto?04/08 at90can32/64/128 figure 19-4. bus arbitration 19.2.5 errors the can protocol signals any errors immediately as they occur. three error detection mecha- nisms are implemented at the message level and two at the bit level: 19.2.5.1 error at message level ? cyclic redundancy check (crc) the crc safeguards the information in the frame by adding redundant check bits at the transmission end. at the receiver these bits are re -computed and tested against the received bits. if they do not agree there has been a crc err or. ? frame check this mechanism verifies the structure of the transm itted frame by checking the bit fields against the fixed format and the frame size. errors detected by frame checks are designated "format errors". ? ack errors as already mentioned frames received are acknowledg ed by all receivers through positive acknowledgement. if no acknowledgement is received by the transmitter of the message an ack error is indicated. 19.2.5.2 error at bit level ? monitoring the ability of the transmitter to detect errors is based on the monitoring of bus signals. each node which transmits also observes the bus level an d thus detects differences between the bit sent and the bit received. this permits reliabl e detection of global errors and errors local to the transmitter. ? bit stuffing the coding of the individual bits is tested at bit level. the bit representation used by can is "non return to zero (nrz)" coding, which guarantees maximum efficiency in bit coding. the synchronization edges are generated by means of bit stuffing. 19.2.5.3 error signalling if one or more errors are discovered by at least on e node using the above mechanisms, the cur- rent transmission is aborted by sending an "error f lag". this prevents other nodes accepting the message and thus ensures the consistency of data th roughout the network. after transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission. node a txcan node b txcan id10 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 sof sof rtr ide can bus - - - - - arbitration lost node a loses the bu node b wins the bus
239 7682c?auto?04/08 at90can32/64/128 19.3 can controller the can controller implemented into at90can32/64/12 8 offers v2.0b active. this full-can controller provides the whole hardwar e for convenient acceptance filtering and message management. for each message to be transmit ted or received this module contains one so called message object in which all informati on regarding the message (e.g. identifier, data bytes etc.) are stored. during the initialization of the peripheral, the ap plication defines which messages are to be sent and which are to be received. only if the can contr oller receives a message whose identifier matches with one of the identifiers of the programm ed (receive-) message objects the message is stored and the application is informed by interr upt. another advantage is that incoming remote frames can be answered automatically by the full-ca n controller with the corresponding data frame. in this way, the cpu load is strongly reduce d compared to a basic-can solution. using full-can controller, high baudrates and high bus loads with many messages can be handled. figure 19-5. can controller structure can channel gen. control gen. status enable mob interrupt bit timing line error can timer lcc mac pls intern txcan intern rxcan m a i l b o x message objets mob0 mob1 mob2 mob14 control status idtag+idmask time stamp control status idtag+idmask time stamp control status idtag+idmask time stamp control status idtag+idmask time stamp buffer mob0 buffer mob1 buffer mob2 buffer mob14 can data buffers size=120 bytes low priority high priority mob scanning
240 7682c?auto?04/08 at90can32/64/128 19.4 can channel 19.4.1 configuration the can channel can be in: ? enabled mode in this mode: ? the can channel (internal txcan & rxcan) is enable d, ? the input clock is enabled. ? standby mode in standby mode: ? the transmitter constantly provides a recessive le vel (on internal txcan) and the receiver is disabled, ? input clock is enabled, ? the registers and pages remain accessible. ? listening mode this mode is transparent for the can channel: ? enables a hardware loop back, internal txcan on in ternal rxcan ? provides a recessive level on txcan output pin ? does not disable rxcan input pin ? freezes tec and rec error counters figure 19-6. listening mode 19.4.2 bit timing fsm?s (finite state machine) of the can channel nee d to be synchronous to the time quantum. so, the input clock for bit timing is the clock use d into can channel fsm?s. field and segment abbreviations: ? brp: baud rate prescaler. ? tq: time quantum (output of baud rate prescaler). ? syns: synchronization segment is 1 tq long. ? prs: propagation time segment is programmable to b e 1, 2, ..., 8 tq long. ? phs1: phase segment 1 is programmable to be 1, 2, ..., 8 tq long. ? phs2: phase segment 2 is programmable to be phs1 and information processing time. ? information processing time is 2 tq. ? sjw: (re) synchronization jump width is programmab le between 1 and min(4, phs1). 1 0 pd5 txcan pd6 rxcan internal txcan internal rxcan listen
241 7682c?auto?04/08 at90can32/64/128 the total number of tq in a bit time has to be prog rammed at least from 8 to 25. figure 19-7. sample and transmission point figure 19-8. general structure of a bit period 19.4.3 baud rate with no baud rate prescaler (brp[5..0]=0) the sampl ing point comes one time quantum too early. this leads to a fail according the iso16845 test plan. it is necessary to lengthen the phase segment 1 by one time quantum and to shorten the phase segment 2 by one time quan- tum to compensate. the baud rate selection is made by t bit calculation: tbit (1) = tsyns + tprs + tphs1 + tphs2 1. tsyns = 1 x tscl = (brp[5..0]+ 1)/clk io (= 1tq) 2. tprs = (1 to 8) x tscl = (prs[2..0]+ 1) x tscl 3. tphs1 = (1 to 8) x tscl = (phs1[2..0]+ 1) x tscl 4. tphs2 = (1 to 8) x tscl = (phs2[2..0] (2) + 1) x tscl bit timing sample point transmission point prescaler brp prs (3-bit length) sjw (2-bit length) phs1 (3-bit length) phs2 (3-bit length) clk io fcan (tscl) time quantum bit rate prescaler clk io f can data tscl (tq) 1 / clk io one nominal bit tsyns (5) tphs2+tsjw ( 4 ) tphs1+tsjw ( 3 ) tbit tphs2 ( 2 ) tphs1 ( 1 ) tprs sample point transmission point 5. synchronization segment: syns tsyns=1 x tscl ( fixed ) notes: 1. phase error < 0 2. phase error > 0 3. phase error > 0 4. phase error < 0 or or
242 7682c?auto?04/08 at90can32/64/128 5. tsjw = (1 to 4) x tscl = (sjw[1..0]+ 1) x tscl notes: 1. the total number of tscl (time quanta) in a bit time must be between 8 to 25. 2. phs2[2..0] 2 is programmable to be phs1[2..0] and 1. 19.4.4 fault confinement (c.f. section 19.7 ?error management? on page 246 ). 19.4.5 overload frame an overload frame is sent by setting an overload re quest (ovrq). after the next reception, the can channel sends an overload frame in accordance w ith the can specification. a status or flag is set (ovrf) as long as the overload frame is sent. figure 19-9. overload frame 19.5 message objects the mob is a can frame descriptor. it contains all information to handle a can frame. this means that a mob has been outlined to allow to desc ribe a can message like an object. the set of mobs is the front end part of the ?mailbox? wher e the messages to send and/or to receive are pre-defined as well as possible to decrease the wor k load of the software. the mobs are numbered from 0 up to 14 (no mob [15]) . they are independent but priority is given to the lower one in case of multi matching. t he operating modes are: ? disabled mode ? transmit mode ? receive mode ? automatic reply ? frame buffer receive mode 19.5.1 operating modes every mob has its own fields to control the operati ng mode. there is no default mode after reset. before enabling the can peripheral, each mob must be configured (ex: disabled mode - conmob=00). ident "a" cmd message data "a" crc interframe a ident "b" overload frame overload frame rxcdan setting ovrq bit ovfg bit resetting ovrq bit txcdan ovrq bit instructions table 19-1. mob configuration mob configuration reply valid rtr tag operating mode 0 0 x x disabled 0 1 x 0 tx data frame x 1 tx remote frame
243 7682c?auto?04/08 at90can32/64/128 19.5.1.1 disabled in this mode, the mob is ?free?. 19.5.1.2 tx data & remote frame 1. several fields must be initialized before sending : ? identifier tag (idt) ? identifier extension (ide) ? remote transmission request (rtrtag) ? data length code (dlc) ? reserved bit(s) tag (rbntag) ? data bytes of message (msg) 2. the mob is ready to send a data or a remote frame when the mob configuration is set (conmob). 3. then, the can channel scans all the mobs in tx co nfiguration, finds the mob having the highest priority and tries to send it. 4. when the transmission is completed the txok flag is set (interrupt). 5. all the parameters and data are available in the mob until a new initialization. 19.5.1.3 rx data & remote frame 1. several fields must be initialized before receivi ng: ? identifier tag (idt) ? identifier mask (idmsk) ? identifier extension (ide) ? identifier extension mask (idemsk) ? remote transmission request (rtrtag) ? remote transmission request mask (rtrmsk) ? data length code (dlc) ? reserved bit(s) tag (rbntag) 2. the mob is ready to receive a data or a remote fr ame when the mob configuration is set (conmob). 3. when a frame identifier is received on can networ k, the can channel scans all the mobs in receive mode, tries to find the mob having the highest priority which is matching. 4. on a hit, the idt, the ide and the dlc of the mat ched mob are updated from the incoming (frame) values. 5. once the reception is completed, the data bytes o f the received message are stored (not for remote frame) in the data buffer of the ma tched mob and the rxok flag is set (interrupt). 1 0 x 0 rx data frame 0 1 rx remote frame 1 rx remote frame then, tx data frame (reply) 1 1 x x frame buffer receive mode table 19-1. mob configuration (continued) mob configuration reply valid rtr tag operating mode
244 7682c?auto?04/08 at90can32/64/128 6. all the parameters and data are available in the mob until a new initialization. 19.5.1.4 automatic reply a reply (data frame) to a remote frame can be autom atically sent after reception of the expected remote frame. 1. several fields must be initialized before receivi ng the remote frame: ? (c.f. section 19.5.1.3 ?rx data & remote frame? on page 2 43 ) 2. when a remote frame matches, automatically the rt rtag and the reply valid bit (rplv) are reset. no flag (or interrupt) is set at this time. since the can data buffer has not been used by the incoming remote frame, the mob is then ready to be in transmit mode without any more setting. the idt, the ide, th e other tags and the dlc of the received remote frame are used for the reply. 3. when the transmission of the reply is completed t he txok flag is set (interrupt). 4. all the parameters and data are available in the mob until a new initialization. 19.5.1.5 frame buffer receive mode this mode is useful to receive multi frames. the pr iority between mobs offers a management for these incoming frames. one set mobs (including non- consecutive mobs) is created when the mobs are set in this mode. due to the mode setting, only one set is possible. a frame buffer completed flag (or interrupt) - bxok - will rise on ly when all the mobs of the set will have received their dedicated can frame. 1. mobs in frame buffer receive mode need to be init ialized as mobs in standard receive mode. 2. the mobs are ready to receive data (or a remote) frames when their respective config- urations are set (conmob). 3. when a frame identifier is received on can networ k, the can channel scans all the mobs in receive mode, tries to find the mob having the highest priority which is matching. 4. on a hit, the idt, the ide and the dlc of the mat ched mob are updated from the incoming (frame) values. 5. once the reception is completed, the data bytes o f the received message are stored (not for remote frame) in the data buffer of the matched mob and the rxok flag is set (interrupt). 6. when the reception in the last mob of the set is completed, the frame buffer completed bxok flag is set (interrupt). bxok flag can be clea red only if all conmob fields of the set have been re-written before. 7. all the parameters and data are available in the mobs until a new initialization. 19.5.2 acceptance filter upon a reception hit (i.e., a good comparison betwe en the i d + rtr + rbn + ide received and an idt+ rtrtag + rbntag + ide specified while taking the comparison mask into ac count) the idt + rtrtag + rbntag + ide received are updated in the mob (written over the registers).
245 7682c?auto?04/08 at90can32/64/128 figure 19-10. acceptance filter block diagram note: examples: full filtering : to accept only id = 0x317 in part a. - id msk = 111 1111 1111 b - id tag = 011 0001 0111 b partiel filtering : to accept id from 0x310 up to 0x317 in part a. - id msk = 111 1111 1000 b - id tag = 011 0001 0xxx b no filtering : to accept all id?s from 0x000 up to 0x7ff in part a. - id msk = 000 0000 0000 b - id tag = xxx xxxx xxxx b 19.5.3 mob page every mob is mapped into a page to save place. the page number is the mob number. this page number is set in canpage register. the number 15 is reserved for factory tests. canhpmob register gives the mob having the highest priority in cansit registers. it is format- ted to provide a direct entry for canpage register. because canhpmob codes cansit registers, it will be only updated if the correspon ding enable bits (enrx, entx, enerr) are enabled (c.f. figure 19-14 ). 19.5.4 can data buffers to preserve register allocation, the can data buffe r is seen such as a fifo (with address pointer accessible) into a mob selection.this also allows to reduce the risks of un-controlled accesses. there is one fifo per mob. this fifo is accessed in to a mob page thanks to the can mes- sage register. the data index (indx) is the address pointer to the required data byte. the data byte can be read or write. the data index is automatically incr emented after every access if the ainc* bit is reset. a roll-over is implemented, after data index =7 it is data index=0. the first byte of a can frame is stored at the data index=0, the second one at the data index=1, ... canidm registers (mob[i]) idmsk rtrmsk idemsk = canidt registers & cancdmob (mob[i]) id &rb rtrtag ide internal rxdcan hit mob[ rx shift register (internal) id &rb rtr ide 13(32) 13(32) 13(32) 13(32) write enable 13(32) 1
246 7682c?auto?04/08 at90can32/64/128 19.6 can timer a programmable 16-bit timer is used for message sta mping and time trigger communication (ttc). figure 19-11. can timer block diagram 19.6.1 prescaler an 8-bit prescaler is initialized by cantcon regist er. it receives the clk io frequency divided by 8. it provides clk cantim frequency to the can timer if the can controller i s enabled. t clk cantim = t clk io x 8 x (cantcon [7:0] + 1) 19.6.2 16-bit timer this timer starts counting from 0x0000 when the can controller is enabled (enfg bit). when the timer rolls over from 0xffff to 0x0000, an inte rrupt is generated (ovrtim). 19.6.3 time triggering two synchronization modes are implemented for ttc ( ttc bit): ? synchronization on start of frame (syncttc=0), ? synchronization on end of frame (syncttc=1). in ttc mode, a frame is sent once, even if an error occurs . 19.6.4 stamping message the capture of the timer value is done in the mob w hich receives or sends the frame. all man- aged mob are stamped, the stamping of a received (s ent) frame occurs on rxok (txok). 19.7 error management 19.7.1 fault confinement the can channel may be in one of the three followin g states: clk io clk cantim cantim canttc canstm[i] cantcon ttc syncttc "eof " "sof " ovrtim txok[i] rxok[i] overrun enfg 8
247 7682c?auto?04/08 at90can32/64/128 ? error active (default): the can channel takes part in bus communication and can send an active error frame when the can macro detects an error. ? error passive: the can channel cannot send an active error frame. it takes part in bus communication, but when an error is detected, a passive error frame is sent. also, after a transmission, an error passive unit will wait before initiating further tr ansmission. ? bus off: the can channel is not allowed to have any influenc e on the bus. for fault confinement, a transmit error counter (te c) and a receive error counter (rec) are implemented. boff and errp bits give the informatio n of the state of the can channel. setting boff to one may generate an interrupt. figure 19-12. line error mode note: more than one rec/tec change may apply during a given message transfer. 19.7.2 error types ? berr : bit error. the bit value which is monitored is di fferent from the bit value sent. note: exceptions: - recessive bit sent monitored as dominant bit duri ng the arbitration field and the acknowl- edge slot. - detecting a dominant bit during the sending of an error frame. ? serr : stuff error. detection of more than five consecut ive bit with the same polarity. ? cerr : crc error (rx only). the receiver performs a crc check on every destuffed received message from the start of frame up to the data fiel d. if this checking does not match with the destuffed crc field, an crc error is set. ? ferr : form error. the form error results from one (or m ore) violations of the fixed form of the following bit fields: ? crc delimiter ? acknowledgement delimiter ? end-of-frame ? error delimiter ? overload delimiter errp = 1 boff = 0 error active error passive bus off tec > 127 or rec > 127 128 occurrences of 1 1 consecutiv recessive bit reset boffit interrupt tec > 255 tec < 127 and rec < 127 errp = 0 boff = 0 errp = 0 boff = 1
248 7682c?auto?04/08 at90can32/64/128 ? aerr : acknowledgment error (tx only). no detection of t he dominant bit in the acknowledge slot. figure 19-13. error detection procedures in a data frame 19.7.3 error setting the can channel can detect some errors on the can n etwork. ? in transmission: the error is set at mob level. ? in reception: - the identified has matched: the error is set at mob level. - the identified has not or not yet matched: the error is set at general level. after detecting an error, the can channel sends an error frame on network. if the can channel detects an error frame on network, it sends its own error frame. 19.8 interrupts 19.8.1 interrupt organization the different interrupts are: ? interrupt on receive completed ok, ? interrupt on transmit completed ok, ? interrupt on error (bit error, stuff error, crc er ror, form error, acknowledge error), ? interrupt on frame buffer full, ? interrupt on ?bus off? setting, ? interrupt on overrun of can timer. the general interrupt enable is provided by enit bi t and the specific interrupt enable for can timer overrun is provided by enorvt bit. identifier message data rtr ack error form error stuff error bit error crc error form error stuff error bit error ack eof sof crc del. ack del. inter. command crc tx rx arbitration
249 7682c?auto?04/08 at90can32/64/128 figure 19-14. can controller interrupt structure 19.8.2 interrupt behavior when an interrupt occurs, an interrupt flag bit is set in the corresponding mob-canstmob reg- ister or in the general cangit register. if in the canie register, enrx / entx / enerr bit are set, then the corresponding mob bit is set in the c ansitn register. to acknowledge a mob interrupt, the corresponding b its of canstmob register (rxok, txok,...) must be cleared by the software applicati on. this operation needs a read-modify-write software routine. to acknowledge a general interrupt, the correspondi ng bits of cangit register (bxok, bof- fit,...) must be cleared by the software applicatio n. this operation is made writing a logical one in these interrupt flags (writing a logical zero do esn?t change the interrupt flag value). ovrtim interrupt flag is reset as the other interru pt sources of cangit register and is also reset entering in its dedicated interrupt handler. when the can node is in transmission and detects a form error in its frame, a bit error will also be raised. consequently, two consecutive interrupts can occur, both due to the same error. when a mob error occurs and is set in its own canst mob register, no general error is set in cangit register. txok[i] canstmob.6 rxok[i] canstmob.5 berr[i] canstmob.4 serr[i] canstmob.3 cerr[i] canstmob.2 ferr[i] canstmob.1 aerr[i] canstmob.0 bxok cangit.4 serg cangit.3 cerg cangit.2 ferg cangit.1 aerg cangit.0 boffi cangit.6 entx cangie.4 enrx cangie.5 enerr cangie.3 enbx cangie.2 energ cangie.1 enboff cangie.6 iemob[i] canie 1/2 enit cangie.7 enovrt cangie.0 sit[i] cansit 1/2 canit cangit.7 can it ovr it i=0 i=14 ovrtim cangit.5
250 7682c?auto?04/08 at90can32/64/128 19.9 can register description figure 19-15. registers organization general control general status general interrupt bit timing 1 bit timing 2 bit timing 3 enable mob 2 enable mob 1 enable interrupt status interrupt mob 2 status interrupt mob 1 enable interrupt mob 2 enable interrupt mob 1 can timer control can ttc low can ttc high can timer low can timer high tec counter rec counter hightest priority mob page mob mob number data index id tag 2 id tag 1 id tag 4 id tag 3 id mask 2 id mask 1 id mask 4 id mask 3 time stamp low time stamp high message data mob status mob control & dlc page mob mob0 - id tag 2 mob0 - id tag 1 mob0 - id tag 4 mob0 - id tag 3 mob0 - id mask 2 mob0 - id mask 1 mob0 - id mask 4 mob0 - id mask 3 mob0 - time stamp low mob0 - time stamp high mob0 - mob status mob0 - mob ctrl & dlc mob0 - mess. data - byte 0 mob14 - id tag 2 mob14 - id tag 1 mob14 - id tag 4 mob14 - id tag 3 mob14 - id mask 2 mob14 - id mask 1 mob14 - id mask 4 mob14 - id mask 3 mob14 - time stamp low mob14 - time stamp high mob14 - mob status mob14 - mob ctrl & dlc mob14 - mess. data - byte 15 message objects 8 bytes a vr registers registers in pages
251 7682c?auto?04/08 at90can32/64/128 19.10 general can registers 19.10.1 can general control register - cangcon ? bit 7 ? abrq: abort request this is not an auto resettable bit. ? 0 - no request. ? 1 - abort request: a reset of canen1 and canen2 re gisters is done. the pending communications are immediately disabled and the on- going one will be normally terminated, setting the appropriate status flags. note that concdmob register remain unchanged. ? bit 6 ? ovrq: overload frame request this is not an auto resettable bit. ? 0 - no request. ? 1 - overload frame request: send an overload frame after the next received frame. the overload frame can be traced observing ovfg in cangsta register (c.f. figure 19-9 on page 242 ). ? bit 5 ? ttc: time trigger communication ? 0 - no ttc. ? 1 - ttc mode. ? bit 4 ? synttc: synchronization of ttc this bit is only used in ttc mode. ? 0 - the ttc timer is caught on sof. ? 1 - the ttc timer is caught on the last bit of the eof. ? bit 3 ? listen: listening mode ? 0 - no listening mode. ? 1 - listening mode. ? bit 2 ? test: test mode ? 0 - no test mode ? 1 - test mode: intend for factory testing and not for customer use. note: can may malfunction if this bit is set. ? bit 1 ? ena/stb : enable / standby mode because this bit is a command and is not immediatel y effective, the enfg bit in cangsta reg- ister gives the true state of the chosen mode. bit 7 6 5 4 3 2 1 0 abrq ovrq ttc synttc listen test ena/stb swres cangcon read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
252 7682c?auto?04/08 at90can32/64/128 ? 0 - standby mode: the on-going communication is no rmally terminated and the can channel is frozen (the conmob bits of every mob do not change). the transmitter constantly provides a recessive level. in this mode , the receiver is not enabled but all the registers and mailbox remain accessible from cpu. ? 1 - enable mode: the can channel enters in enable mode once 11 recessive bits has been read. ? bit 0 ? swres: software reset request this auto resettable bit only resets the can contro ller. ? 0 - no reset ? 1 - reset: this reset is ?ored? with the hardware reset. 19.10.2 can general status register - cangsta ? bit 7 ? reserved bit this bit is reserved for future use. ? bit 6 ? ovfg: overload frame flag this flag does not generate an interrupt. ? 0 - no overload frame. ? 1 - overload frame: set by hardware as long as the produced overload frame is sent. ? bit 5 ? reserved bit this bit is reserved for future use. ? bit 4 ? txbsy: transmitter busy this flag does not generate an interrupt. ? 0 - transmitter not busy. ? 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or error frame) or an ack field is sent. also set when an inter frame space is sent. ? bit 3 ? rxbsy: receiver busy this flag does not generate an interrupt. ? 0 - receiver not busy ? 1 - receiver busy: set by hardware as long as a fr ame is received or monitored. ? bit 2 ? enfg: enable flag this flag does not generate an interrupt. ? 0 - can controller disable: because an enable/stan dby command is not immediately effective, this status gives the true state of the chosen mode. ? 1 - can controller enable. bit 7 6 5 4 3 2 1 0 - ovfg - txbsy rxbsy enfg boff errp cangsta read/write - r - r r r r r initial value - 0 - 0 0 0 0 0
253 7682c?auto?04/08 at90can32/64/128 ? bit 1 ? boff: bus off mode boff gives the information of the state of the can channel. only entering in bus off mode gen- erates the boffit interrupt. ? 0 - no bus off mode. ? 1 - bus off mode. ? bit 0 ? errp: error passive mode errp gives the information of the state of the can channel. this flag does not generate an interrupt. ? 0 - no error passive mode. ? 1 - error passive mode. 19.10.3 can general interrupt register - cangit ? bit 7 ? canit: general interrupt flag this is a read only bit. ? 0 - no interrupt. ? 1 - can interrupt: image of all the can controller interrupts except for ovrtim interrupt. this bit can be used for polling method. ? bit 6 ? boffit: bus off interrupt flag writing a logical one resets this interrupt flag. b offit flag is only set when the can enters in bus off mode (coming from error passive mode). ? 0 - no interrupt. ? 1 - bus off interrupt when the can enters in bus o ff mode. ? bit 5 ? ovrtim: overrun can timer writing a logical one resets this interrupt flag. e ntering in can timer overrun interrupt handler also reset this interrupt flag ? 0 - no interrupt. ? 1 - can timer overrun interrupt: set when the can timer switches from 0xffff to 0. ? bit 4 ? bxok: frame buffer receive interrupt writing a logical one resets this interrupt flag. b xok flag can be cleared only if all conmob fields of the mob?s of the buffer have been re-writ ten before. ? 0 - no interrupt. ? 1 - burst receive interrupt: set when the frame bu ffer receive is completed. ? bit 3 ? serg: stuff error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. bit 7 6 5 4 3 2 1 0 canit boffit ovrtim bxok serg cerg ferg aerg cangit read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
254 7682c?auto?04/08 at90can32/64/128 ? 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same polarity. ? bit 2 ? cerg: crc error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. ? 1 - crc error interrupt: the crc check on destuffe d message does not fit with the crc field. ? bit 1 ? ferg: form error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. ? 1 - form error interrupt: one or more violations o f the fixed form in the crc delimiter, acknowledgment delimiter or eof. ? bit 0 ? aerg: acknowledgment error general writing a logical one resets this interrupt flag. ? 0 - no interrupt. ? 1 - acknowledgment error interrupt: no detection o f the dominant bit in acknowledge slot. 19.10.4 can general interrupt enable register - cang ie ? bit 7 ? enit: enable all interrupts (except for can timer overrun interrupt) ? 0 - interrupt disabled. ? 1- canit interrupt enabled. ? bit 6 ? enboff: enable bus off interrupt ? 0 - interrupt disabled. ? 1- bus off interrupt enabled. ? bit 5 ? enrx: enable receive interrupt ? 0 - interrupt disabled. ? 1- receive interrupt enabled. ? bit 4 ? entx: enable transmit interrupt ? 0 - interrupt disabled. ? 1- transmit interrupt enabled. ? bit 3 ? enerr: enable mob errors interrupt ? 0 - interrupt disabled. ? 1- mob errors interrupt enabled. bit 7 6 5 4 3 2 1 0 enit enboff enrx entx enerr enbx energ enovrt cangie read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
255 7682c?auto?04/08 at90can32/64/128 ? bit 2 ? enbx: enable frame buffer interrupt ? 0 - interrupt disabled. ? 1- frame buffer interrupt enabled. ? bit 1 ? energ: enable general errors interrupt ? 0 - interrupt disabled. ? 1- general errors interrupt enabled. ? bit 0 ? enovrt: enable can timer overrun interrupt ? 0 - interrupt disabled. ? 1- can timer interrupt overrun enabled. 19.10.5 can enable mob registers - canen2 and canen1 ? bits 14:0 - enmob14:0: enable mob this bit provides the availability of the mob. it is set to one when the mob is enabled (i.e. conm ob1:0 of cancdmob register). once txok or rxok is set to one (txok for automatic reply), the corresponding enmob is reset. enmob is also set to zero configuring the mo b in disabled mode, applying abortion or standby mode. ? 0 - message object disabled: mob available for a n ew transmission or reception. ? 1 - message object enabled: mob in use. ? bit 15 ? reserved bit this bit is reserved for future use. 19.10.6 can enable interrupt mob registers - canie2 and canie1 bit 7 6 5 4 3 2 1 0 enmob7 enmob6 enmob5 enmob4 enmob3 enmob2 enmob1 enmob0 can en2 - enmob14 enmob13 enmob12 enmob11 enmob10 enmob9 enmob8 can en1 bit 15 14 13 12 11 10 9 8 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 read/write - r r r r r r r initial value - 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 iemob7 iemob6 iemob5 iemob4 iemob3 iemob2 iemob1 iemob0 can ie2 - iemob14 iemob13 iemob12 iemob11 iemob10 iemob9 iemob8 can ie1 bit 15 14 13 12 11 10 9 8 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 read/write - r/w r/w r/w r/w r/w r/w r/w initial value - 0 0 0 0 0 0 0
256 7682c?auto?04/08 at90can32/64/128 ? bits 14:0 - iemob14:0: interrupt enable by mob ? 0 - interrupt disabled. ? 1 - mob interrupt enabled note: example: canie2 = 0000 1100 b : enable of interrupts on mob 2 & 3. ? bit 15 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canie1 is written. 19.10.7 can status interrupt mob registers - cansit2 and cansit1 ? bits 14:0 - sit14:0: status of interrupt by mob ? 0 - no interrupt. ? 1- mob interrupt. note: example: cansit2 = 0010 0001 b : mob 0 & 5 interrupts. ? bit 15 ? reserved bit this bit is reserved for future use. 19.10.8 can bit timing register 1 - canbt1 ? bit 7? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canbt1 is written. ? bit 6:1 ? brp5:0: baud rate prescaler the period of the can controller system clock tscl is programmable and determines the individ- ual bit timing. if brp[5..0]=0, see section 19.4.3 ?baud rate? on page 241 . ? bit 0 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canbt1 is written. bit 7 6 5 4 3 2 1 0 sit7 sit6 sit5 sit4 sit3 sit2 sit1 sit0 cansit2 - sit14 sit13 sit12 sit11 sit10 sit9 sit8 cansit1 bit 15 14 13 12 11 10 9 8 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 read/write - r r r r r r r initial value - 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 - brp5 brp4 brp3 brp2 brp1 brp0 - canbt1 read/write - r/w r/w r/w r/w r/w r/w - initial value - 0 0 0 0 0 0 - tscl = brp[5:0] + 1 clk io frequency
257 7682c?auto?04/08 at90can32/64/128 19.10.9 can bit timing register 2 - canbt2 ? bit 7? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canbt2 is written. ? bit 6:5 ? sjw1:0: re-synchronization jump width to compensate for phase shifts between clock oscill ators of different bus controllers, the control- ler must re-synchronize on any relevant signal edge of the current transmission. the synchronization jump width defines the maximum number of clock cycles. a bit period may be shortened or lengthened by a re-synchronization. ? bit 4 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canbt2 is written. ? bit 3:1 ? prs2:0: propagation time segment this part of the bit time is used to compensate for the physical delay times within the network. it is twice the sum of the signal propagation time on the bus line, the input comparator delay and the output driver delay. ? bit 0 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canbt2 is written. 19.10.10 can bit timing register 3 - canbt3 ? bit 7? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canbt3 is written. ? bit 6:4 ? phs22:0: phase segment 2 this phase is used to compensate for phase edge err ors. this segment may be shortened by the re-synchronization jump width. phs2[2..0] shall be 1 and phs1[2..0] (c.f. section 19.2.3 ?can bit timing? on page 235 and section 19.4.3 ?baud rate? on page 241 ). bit 7 6 5 4 3 2 1 0 - sjw1 sjw0 - prs2 prs1 prs0 - canbt2 read/write - r/w r/w - r/w r/w r/w - initial value - 0 0 - 0 0 0 - tsjw = tscl x (sjw [1:0] +1) tprs = tscl x (prs [2:0] + 1) bit 7 6 5 4 3 2 1 0 - phs22 phs21 phs20 phs12 phs11 phs10 smp canbt3 read/write - r/w r/w r/w r/w r/w r/w r/w initial value - 0 0 0 0 0 0 0 tphs2 = tscl x (phs2 [2:0] + 1)
258 7682c?auto?04/08 at90can32/64/128 ? bit 3:1 ? phs12:0: phase segment 1 this phase is used to compensate for phase edge err ors. this segment may be lengthened by the re-synchronization jump width. ? bit 0 ? smp: sample point(s) ? 0 - once, at the sample point. ? 1 - three times, the threefold sampling of the bus is the sample point and twice over a distance of a 1/2 period of the tscl. the result corresponds to the majority decision of the three values. 19.10.11 can timer control register - cantcon ? bit 7:0 ? tprsc7:0: can timer prescaler prescaler for the can timer upper counter range 0 t o 255. it provides the clock to the can timer if the can controller is enabled. t clk cantim = t clk io x 8 x (cantcon [7:0] + 1) 19.10.12 can timer registers - cantiml and cantimh ? bits 15:0 - cantim15:0: can timer count can timer counter range 0 to 65,535. 19.10.13 can ttc timer registers - canttcl and cantt ch ? bits 15:0 - timttc15:0: ttc timer count can ttc timer counter range 0 to 65,535. tphs1 = tscl x (phs1 [2:0] + 1) bit 7 6 5 4 3 2 1 0 tprsc7 tprsc6 tprsc5 tprsc4 tprsc3 tprsc2 trpsc1 tprsc0 can tcon read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 cantim7 cantim6 cantim5 cantim4 cantim3 cantim2 cantim1 ca ntim0 cantiml cantim15 cantim14 cantim13 cantim12 cantim11 cantim10 can tim9 cantim8 cantimh bit 15 14 13 12 11 10 9 8 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 timttc7 timttc6 timttc5 timttc4 timttc3 timttc2 timttc1 ti mttc0 canttcl timttc15 timttc14 timttc13 timttc12 timttc11 timttc10 tim ttc9 timttc8 canttch bit 15 14 13 12 11 10 9 8 read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0
259 7682c?auto?04/08 at90can32/64/128 19.10.14 can transmit error counter register - cante c ? bit 7:0 ? tec7:0: transmit error count can transmit error counter range 0 to 255. 19.10.15 can receive error counter register - canrec ? bit 7:0 ? rec7:0: receive error count can receive error counter range 0 to 255. 19.10.16 can highest priority mob register - canhpmo b ? bit 7:4 ? hpmob3:0: highest priority mob number mob having the highest priority in cansit registers . if cansit = 0 (no mob), the return value is 0xf. note: do not confuse ?mob priority? and ?message id priority?. ? bit 3:0 ? cgp3:0: can general purpose bits these bits can be pre-programmed to match with the wanted configuration of the canpage register (i.e., ainc and indx2:0 setting). 19.10.17 can page mob register - canpage ? bit 7:4 ? mobnb3:0: mob number selection of the mob number, the available numbers are from 0 to 14. ? bit 3 ? ainc : auto increment of the fifo can data buffer index (active low) ? 0 - auto increment of the index (default value). ? 1- no auto increment of the index. ? bit 2:0 ? indx2:0: fifo can data buffer index byte location of the can data byte into the fifo fo r the defined mob. bit 7 6 5 4 3 2 1 0 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 cantec read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 canrec read/write r r r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 hpmob3 hpmob2 hpmob1 hpmob0 cgp3 cgp 2 cgp 1 cgp 0 canhpmob read/write r r r r r/w r/w r/w r/w initial value 1 1 1 1 0 0 0 0 bit 7 6 5 4 3 2 1 0 mobnb3 mobnb2 mobnb1 mobnb0 ainc indx2 indx1 indx0 canpage read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
260 7682c?auto?04/08 at90can32/64/128 19.11 mob registers the mob registers has no initial (default) value after reset. 19.11.1 can mob status register - canstmob ? bit 7 ? dlcw: data length code warning the incoming message does not have the dlc expected . whatever the frame type, the dlc field of the cancdmob register is updated by the re ceived dlc. ? bit 6 ? txok: transmit ok this flag can generate an interrupt. it must be cle ared using a read-modify-write software routine on the whole canstmob register. the communication enabled by transmission is comple ted. txok rises at the end of eof field. when the controller is ready to send a frame, if tw o or more message objects are enabled as producers, the lower mob index (0 to 14) is supplie d first. ? bit 5 ? rxok: receive ok this flag can generate an interrupt. it must be cle ared using a read-modify-write software routine on the whole canstmob register. the communication enabled by reception is completed . rxok rises at the end of the 6 th bit of eof field. in case of two or more message object re ception hits, the lower mob index (0 to 14) is updated first. ? bit 4 ? berr: bit error (only in transmission) this flag can generate an interrupt. it must be cle ared using a read-modify-write software routine on the whole canstmob register. the bit value monitored is different from the bit v alue sent. exceptions: the monitored recessive bit sent as a d ominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during th e sending of an error frame. ? bit 3 ? serr: stuff error this flag can generate an interrupt. it must be cle ared using a read-modify-write software routine on the whole canstmob register. detection of more than five consecutive bits with t he same polarity. this flag can generate an interrupt. ? bit 2 ? cerr: crc error this flag can generate an interrupt. it must be cle ared using a read-modify-write software routine on the whole canstmob register. the receiver performs a crc check on every de-stuff ed received message from the start of frame up to the data field. if this checking does n ot match with the de-stuffed crc field, a crc error is set. bit 7 6 5 4 3 2 1 0 dlcw txok rxok berr serr cerr ferr aerr canstmob read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - -
261 7682c?auto?04/08 at90can32/64/128 ? bit 1 ? ferr: form error this flag can generate an interrupt. it must be cle ared using a read-modify-write software routine on the whole canstmob register. the form error results from one or more violations of the fixed form in the following bit fields: ? crc delimiter. ? acknowledgment delimiter. ? eof ? bit 0 ? aerr: acknowledgment error this flag can generate an interrupt. it must be cle ared using a read-modify-write software routine on the whole canstmob register. no detection of the dominant bit in the acknowledge slot. 19.11.2 can mob control and dlc register - cancdmob ? bit 7:6 ? conmob1:0: configuration of message obje ct these bits set the communication to be performed ( no initial value after reset). ? 00 - disable. ? 01 - enable transmission. ? 10 - enable reception. ? 11 - enable frame buffer reception these bits are not cleared once the communication is performed. the u ser must re-write the configuration to enable a new communication. ? this operation is necessary to be able to reset th e bxok flag. ? this operation also set the corresponding bit in t he canen registers. ? bit 5 ? rplv: reply valid used in the automatic reply mode after receiving a remote frame. ? 0 - reply not ready. ? 1 - reply ready and valid. ? bit 4 ? ide: identifier extension ide bit of the remote or data frame to send. this bit is updated with the corresponding value of the remote or data frame received. ? 0 - can standard rev 2.0 a (identifiers length = 1 1 bits). ? 1 - can standard rev 2.0 b (identifiers length = 2 9 bits). ? bit 3:0 ? dlc3:0: data length code number of bytes in the data field of the message. bit 7 6 5 4 3 2 1 0 conmob1 conmob0 rplv ide dlc3 dlc2 dlc1 dlc0 cancdmob read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - -
262 7682c?auto?04/08 at90can32/64/128 dlc field of the remote or data frame to send. the range of dlc is from 0 up to 8. if dlc field >8 then effective dlc=8. this field is updated with the corresponding value of the remote or data frame received. if the expected dlc differs from the incoming dlc, a dlc w arning appears in the canstmob register. 19.11.3 can identifier tag registers - canidt1, canidt2, canidt3, and canidt4 v2.0 part a v2.0 part b v2.0 part a ? bit 31:21 ? idt10:0: identifier tag identifier field of the remote or data frame to sen d. this field is updated with the corresponding value of the remote or data frame received. ? bit 20:3 ? reserved bits these bits are reserved for future use. for compati bility with future devices, they must be written to zero when canidtn are written. when a remote or data frame is received, these bits do not operate in the comparison but they are updated with un-predicted values. ? bit 2 ? rtrtag: remote transmission request tag rtr bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. in case of automatic reply mode, this bit is automatically reset before sending the response. ? bit 1 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canidtn are written. bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - rtrtag - rb0tag canidt4 - - - - - - - - canidt3 idt 2 idt 1 idt 0 - - - - - canidt2 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 idt 4 idt 3 canidt1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 idt 4 idt 3 idt 2 idt 1 idt 0 rtrtag rb1tag rb0tag canidt4 idt 12 idt 11 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 canidt3 idt 20 idt 19 idt 18 idt 17 idt 16 idt 15 idt 14 idt 13 canidt2 idt 28 idt 27 idt 26 idt 25 idt 24 idt 23 idt 22 idt 21 canidt1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - -
263 7682c?auto?04/08 at90can32/64/128 when a remote or data frame is received, this bit d oes not operate in the comparison but it is updated with un-predicted values. ? bit 0 ? rb0tag: reserved bit 0 tag rb0 bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. v2.0 part b ? bit 31:3 ? idt28:0: identifier tag identifier field of the remote or data frame to sen d. this field is updated with the corresponding value of the remote or data frame received. ? bit 2 ? rtrtag: remote transmission request tag rtr bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. in case of automatic reply mode, this bit is automatically reset before sending the response. ? bit 1 ? rb1tag: reserved bit 1 tag rb1 bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. ? bit 0 ? rb0tag: reserved bit 0 tag rb0 bit of the remote or data frame to send. this tag is updated with the corresponding value of the remote or data frame received. 19.11.4 can identifier mask registers - canidm1, canidm2, canidm3, and canidm4 v2.0 part a v2.0 part b bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - rtrmsk - idemsk canidm4 - - - - - - - - canidm3 idmsk 2 idmsk 1 idmsk 0 - - - - - canidm2 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 idmsk 4 idmsk 3 canidm1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 idmsk 4 idmsk 3 idmsk 2 idmsk 1 idmsk 0 rtrmsk - idemsk canidm4 idmsk 12 idmsk 11 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 canidm3 idmsk 20 idmsk 19 idmsk 18 idmsk 17 idmsk 16 idmsk 15 idmsk 14 idmsk 13 canidm2 idmsk 28 idmsk 27 idmsk 26 idmsk 25 idmsk 24 idmsk 23 idmsk 22 idmsk 21 canidm1 bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - -
264 7682c?auto?04/08 at90can32/64/128 v2.0 part a ? bit 31:21 ? idmsk10:0: identifier mask ? 0 - comparison true forced ? 1 - bit comparison enabled. ? bit 20:3 ? reserved bits these bits are reserved for future use. for compati bility with future devices, they must be written to zero when canidmn are written. ? bit 2 ? rtrmsk: remote transmission request mask ? 0 - comparison true forced ? 1 - bit comparison enabled. ? bit 1 ? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when canidtn are written. ? bit 0 ? idemsk: identifier extension mask ? 0 - comparison true forced ? 1 - bit comparison enabled. v2.0 part b ? bit 31:3 ? idmsk28:0: identifier mask ? 0 - comparison true forced ? 1 - bit comparison enabled. ? bit 2 ? rtrmsk: remote transmission request mask ? 0 - comparison true forced ? 1 - bit comparison enabled. ? bit 1 ? reserved bit writing zero in this bit is recommended. ? bit 0 ? idemsk: identifier extension mask ? 0 - comparison true forced ? 1 - bit comparison enabled. 19.11.5 can time stamp registers - canstml and canst mh ? bits 15:0 - timstm15:0: time stamp count can time stamp counter range 0 to 65,535. bit 7 6 5 4 3 2 1 0 timstm7 timstm6 timstm5 timstm4 timstm3 timstm2 timstm1 ti mstm0 canstml timstm15 timstm14 timstm13 timstm12 timstm11 timstm10 tim stm9 timstm8 canstmh bit 15 14 13 12 11 10 9 8 read/write r r r r r r r r initial value - - - - - - - -
265 7682c?auto?04/08 at90can32/64/128 19.11.6 can data message register - canmsg ? bit 7:0 ? msg7:0: message data this register contains the can data byte pointed at the page mob register. after writing in the page mob register, this byte i s equal to the specified message location of the pre-defined identifier + index. if auto-incrementat ion is used, at the end of the data register writ- ing or reading cycle, the index is auto-incremented . the range of the counting is 8 with no end of loop (0, 1,..., 7, 0,...). 19.12 examples of can baud rate setting the can bus requires very accurate timing especiall y for high baud rates. it is recommended to use only an external crystal for can operations. (refer to ?bit timing? on page 240 and ?baud rate? on page 241 for timing description and page 256 to page 257 for ?can bit timing registers?). bit 7 6 5 4 3 2 1 0 msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 canmsg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value - - - - - - - - table 19-2. examples of can baud rate settings for commonly fre quencies f clk io (mhz) can baud rate (kbps) description segments registers sampling point tq (s) tbit (tq) tprs (tq) tph1 (tq) tph2 (tq) tsjw (tq) canbt1 canbt2 canbt3 16.000 1000 69 % (1) 0.0625 16 7 4 4 1 0x00 0x0c 0x37 75 % 0.125 8 3 2 2 1 0x02 0x04 0x13 500 75 % 0.125 16 7 4 4 1 0x02 0x0c 0x37 0.250 8 3 2 2 1 0x06 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x06 0x0c 0x37 0.500 8 3 2 2 1 0x0e 0x04 0x13 200 75 % 0.3125 16 7 4 4 1 0x08 0x0c 0x37 0.625 8 3 2 2 1 0x12 0x04 0x13 125 75 % 0.500 16 7 4 4 1 0x0e 0x0c 0x37 1.000 8 3 2 2 1 0x1e 0x04 0x13 100 75 % 0.625 16 7 4 4 1 0x12 0x0c 0x37 1.250 8 3 2 2 1 0x26 0x04 0x13
266 7682c?auto?04/08 at90can32/64/128 12.000 1000 67 % (1) 0.083333 12 5 3 3 1 0x00 0x08 0x25 x - - - n o d a t a - - - 500 75 % 0.166666 12 5 3 3 1 0x02 0x08 0x25 0.250 8 3 2 2 1 0x04 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x04 0x0c 0x37 0.500 8 3 2 2 1 0x0a 0x04 0x13 200 75 % 0.250 20 8 6 5 1 0x04 0x0e 0x4b 0.416666 12 5 3 3 1 0x08 0x08 0x25 125 75 % 0.500 16 7 4 4 1 0x0a 0x0c 0x37 1.000 8 3 2 2 1 0x16 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x0a 0x0e 0x4b 0.833333 12 5 3 3 1 0x12 0x08 0x25 8.000 1000 63 % (1) x - - - n o d a t a - - - 0.125 8 3 2 2 1 0x00 0x04 0x13 500 69 % (1) 0.125 16 7 4 4 1 0x00 0x0c 0x37 75 % 0.250 8 3 2 2 1 0x02 0x04 0x13 250 75 % 0.250 16 7 4 4 1 0x02 0x0c 0x37 0.500 8 3 2 2 1 0x06 0x04 0x13 200 75 % 0.250 20 8 6 5 1 0x02 0x0e 0x4b 0.625 8 3 2 2 1 0x08 0x04 0x13 125 75 % 0.500 16 7 4 4 1 0x06 0x0c 0x37 1.000 8 3 2 2 1 0x0e 0x04 0x13 100 75 % 0.625 16 7 4 4 1 0x08 0x0c 0x37 1.250 8 3 2 2 1 0x12 0x04 0x13 table 19-2. examples of can baud rate settings for commonly fre quencies (continued) f clk io (mhz) can baud rate (kbps) description segments registers sampling point tq (s) tbit (tq) tprs (tq) tph1 (tq) tph2 (tq) tsjw (tq) canbt1 canbt2 canbt3
267 7682c?auto?04/08 at90can32/64/128 note: 1. see section 19.4.3 ?baud rate? on page 241 . 6.000 1000 - - - n o t a p p l i c a b l e - - - 500 67 % (1) 0.166666 12 5 3 3 1 0x00 0x08 0x25 x - - - n o d a t a - - - 250 75 % 0.333333 12 5 3 3 1 0x02 0x08 0x25 0.500 8 3 2 2 1 0x04 0x04 0x13 200 80 % 0.333333 15 7 4 3 1 0x02 0x0c 0x35 0.500 10 4 3 2 1 0x04 0x06 0x23 125 75 % 0.500 16 7 4 4 1 0x04 0x0c 0x37 1.000 8 3 2 2 1 0x0a 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x04 0x0e 0x4b 0.833333 12 5 3 3 1 0x08 0x08 0x25 4.000 1000 - - - n o t a p p l i c a b l e - - - 500 63 % (1) x - - - n o d a t a - - - 0.250 8 3 2 2 1 0x00 0x04 0x13 250 69 % (1) 0.250 16 7 4 4 1 0x00 0x0c 0x37 75 % 0.500 8 3 2 2 1 0x02 0x04 0x13 200 70 % (1) 0.250 20 8 6 5 1 0x00 0x0e 0x4b x - - - n o d a t a - - - 125 75 % 0.500 16 7 4 4 1 0x02 0x0c 0x37 1.000 8 3 2 2 1 0x06 0x04 0x13 100 75 % 0.500 20 8 6 5 1 0x02 0x0e 0x4b 1.250 8 3 2 2 1 0x08 0x04 0x13 table 19-2. examples of can baud rate settings for commonly fre quencies (continued) f clk io (mhz) can baud rate (kbps) description segments registers sampling point tq (s) tbit (tq) tprs (tq) tph1 (tq) tph2 (tq) tsjw (tq) canbt1 canbt2 canbt3
268 7682c?auto?04/08 at90can32/64/128 20. analog comparator the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. 20.1 overview when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comp arator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate inter- rupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 20-1 . figure 20-1. analog comparator block diagram (1)(2) notes: 1. adc multiplexer output: see table 20-2 on page 270 . 2. refer to figure 1-2 on page 5 and table 9-15 on page 83 for analog comparator pin placement. 20.2 analog comparator register description 20.2.1 adc control and status register b ? adcsrb ? bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is s witched off (aden in adcsra is zero), the adc multiplexer selects the negative input to the a nalog comparator. when this bit is written logic zero, ain1 is applied to the negative input o f the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 270 . acbg bandgap reference adc multiplexer output acme aden t/c1 input capture bit 7 6 5 4 3 2 1 0 - acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0
269 7682c?auto?04/08 at90can32/64/128 20.2.2 analog comparator control and status register ? acsr ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to th e analog comparator is switched off. this bit can be set at any time to turn off the analog compa rator. this will reduce power consumption in active and idle mode. when changing the acd bit, th e analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwis e an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference vol tage replaces the positive input to the analog comparator. when this bit is cleared, ain0 is appli ed to the positive input of the analog compar- ator. see ?internal voltage reference? on page 56. ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock c ycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator outpu t event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by har dware when executing the corresponding inter- rupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bi t in the status register is set, the analog com- parator interrupt is activated. when written logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enab le when written logic one, this bit enables the input capture function in timer/counter1 to be trig- gered by the analog comparator. the comparator outp ut is in this case directly connected to the input capture front-end logic, making the comparato r utilize the noise canceler and edge select features of the timer/counter1 input capture interr upt. when written logic zero, no connection between the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. bit 7 6 5 4 3 2 1 0 acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 n/a 0 0 0 0 0
270 7682c?auto?04/08 at90can32/64/128 ? bits 1, 0 ? acis1, acis0: analog comparator interr upt mode select these bits determine which comparator events that t rigger the analog comparator interrupt. the different settings are shown in table 20-1 . when changing the acis1/acis0 bits, the analog comp arator interrupt must be disabled by clearing its interrupt enable bit in the acsr regis ter. otherwise an interrupt can occur when the bits are changed. 20.3 analog comparator multiplexed input it is possible to select any of the adc7..0 pins to replace the negative input to the analog com- parator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (aden in adcsra is zero), mux2..0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 20-2 . if acme is cleared or aden is set, ain1 is applie d to the negative input to the analog comparator. table 20-1. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 0 1 reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. table 20-2. analog comparator multiplexed input acme aden mux2..0 analog comparator negative input 0 x xxx ain1 1 1 xxx ain1 1 0 000 adc0 1 0 001 adc1 1 0 010 adc2 1 0 011 adc3 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7
271 7682c?auto?04/08 at90can32/64/128 20.3.1 digital input disable register 1 ? didr1 ? bit 1, 0 ? ain1d, ain0d: ain1, ain0 digital input disable when this bit is written logic one, the digital inp ut buffer on the ain1/0 pin is disabled. the corre- sponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain1/0 pin and the digital input fro m this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the di gital input buffer. bit 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ain1d ain0d didr1 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0
272 7682c?auto?04/08 at90can32/64/128 21. analog to digital converter - adc 21.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 13 - 260 s conversion time ? up to 76 ksps at maximum resolution ? eight multiplexed single ended input channels ? seven differential input channels ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 2.56 v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto triggering on interrup t sources ? interrupt on adc conversion complete ? sleep mode noise canceler the at90can32/64/128 features a 10-bit successive a pproximation adc. the adc is con- nected to an 8-channel analog multiplexer which all ows eight single-ended voltage inputs constructed from the pins of port f. the single-end ed voltage inputs refer to 0v (gnd). the device also supports 16 differential voltage in put combinations. two of the differential inputs (adc1, adc0 and adc3, adc2) are equipped with a pro grammable gain stage, providing amplification steps of 0 db (1x), 20 db (10x), or 4 6 db (200x) on the differential input voltage before the a/d conversion. seven differential analo g input channels share a common negative terminal (adc1), while any other adc input can be s elected as the positive input terminal. if 1x or 10x gain is used, 8-bit resolution can be expect ed. if 200x gain is used, 7-bit resolution can be expected. the adc contains a sample and hold circuit which en sures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 21-1 . the adc has a separate analog supply voltage pin, a v cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 279 on how to connect this pin. internal reference voltages of nominally 2.56v or a v cc are provided on-chip. the voltage refer- ence may be externally decoupled at the aref pin by a capacitor for better noise performance.
273 7682c?auto?04/08 at90can32/64/128 figure 21-1. analog to digital converter block schematic 21.2 operation the adc converts an analog input voltage to a 10-bi t digital value through successive approxi- mation. the minimum value represents gnd and the ma ximum value represents the voltage on adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample & hold comparator internal reference mux decoder mux4 avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output differential amplifier aref bandgap reference prescaler single ended / differential selection gnd pos. input mux neg. input mux trigger select adts[2:0] interrupt flags start
274 7682c?auto?04/08 at90can32/64/128 the aref pin minus 1 lsb. optionally, av cc or an internal 2.56v reference voltage may be con- nected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an exter nal capacitor at the aref pin to improve noise immunity. the analog input channel and differential gain are selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd an d a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. a se lection of adc input pins can be selected as positive and negative inputs to the differential am plifier. the adc is enabled by setting the adc enable bit, a den in adcsra. voltage reference and input channel selections will not go into effect un til aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presente d in the adc data registers, adch and adcl. by default, the result is presented right adj usted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-b it precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch , to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result fr om the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-ena bled. the adc has its own interrupt which can be triggere d when a conversion completes. the adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 21.3 starting a conversion a single conversion is started by writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. if a different da ta channel is selected while a conversion is in progress, the adc will finish the current conversio n before performing the channel change. alternatively, a conversion can be triggered automa tically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, ad ts in adcsrb (see description of the adts bits for a list of the trigger sources). when a pos itive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is star ted. this provides a method of starting con- versions at fixed intervals. if the trigger signal is still set when the conversion completes, a new conversion will not be started. if another positive edge occurs on the trigger signal during con- version, the edge will be ignored. note that an int errupt flag will be set even if the specific interrupt is disabled or the global interrupt enabl e bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt even t.
275 7682c?auto?04/08 at90can32/64/128 figure 21-2. adc auto trigger logic using the adc interrupt flag as a trigger source ma kes the adc start a new conversion as soon as the ongoing conversion has finished. the adc the n operates in free running mode, con- stantly sampling and updating the adc data register . the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successive conversions independently of whether the adc interr upt flag, adif is cleared or not. if auto triggering is enabled, single conversions c an be started by writing adsc in adcsra to one. adsc can also be used to determine if a conver sion is in progress. the adsc bit will be read as one during a conversion, independently of h ow the conversion was started. 21.4 prescaling and conversion timing figure 21-3. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a low er resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. the adc module contains a prescaler, which generate s an acceptable adc clock frequency from any cpu frequency above 100 khz. the prescalin g is set by the adps bits in adcsra. the prescaler starts counting from the moment the a dc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start
276 7682c?auto?04/08 at90can32/64/128 when initiating a single ended conversion by settin g the adsc bit in adcsra, the conversion starts at the following rising edge of the adc cloc k cycle. see ?differential channels? on page 277 for details on differential conversion timing. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycle s in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc cloc k cycles after the start of a normal conver- sion and 13.5 adc clock cycles after the start of a n first conversion. when a conversion is complete, the result is written to the adc data reg isters, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be initiated on the first rising ad c clock edge. when auto triggering is used, the prescaler is rese t when the trigger event occurs. this assures a fixed delay from the trigger event to the start o f conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising e dge on the trigger source signal. three addi- tional cpu clock cycles are used for synchronizatio n logic. in free running mode, a new conversion will be star ted immediately after the conversion com- pletes, while adsc remains high. for a summary of c onversion times, see table 21-1 . figure 21-4. adc timing diagram, first conversion (single conver sion mode) figure 21-5. adc timing diagram, single conversion sign and msb of resul lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 1 2 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update
277 7682c?auto?04/08 at90can32/64/128 figure 21-6. adc timing diagram, auto triggered conversion figure 21-7. adc timing diagram, free running conversion 21.4.1 differential channels when using differential channels, certain aspects o f the conversion need to be taken into consideration. differential conversions are synchronized to the in ternal clock ck adc2 equal to half the adc clock frequency. this synchronization is done autom atically by the adc interface in such a way that the sample-and-hold occurs at a specific phase of ck adc2 . a conversion initiated by the user (i.e., all single conversions, and the first f ree running conversion) when ck adc2 is low will take the same amount of time as a single ended conv ersion (13 adc clock cycles from the next prescaled clock cycle). a conversion initiated by t he user when ck adc2 is high will take 14 adc clock cycles due to the synchronization mechanism. in free running mode, a new conversion is table 21-1. adc conversion time condition first conversion normal conversion, single ended auto triggered conversion sample & hold (cycles from start of convention) 14.5 1.5 2 conversion time (cycles) 25 13 13.5 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of resu lsb of result adc clock trigger source adif adch adcl cycle number 1 2 one conversion next conversi conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 1 2 one conversion next conversion 3 4 conversion complete sample & hol mux and refs update
278 7682c?auto?04/08 at90can32/64/128 initiated immediately after the previous conversion completes, and since ck adc2 is high at this time, all automatically started (i.e., all but the first) free running conversions will take 14 adc clock cycles. if differential channels are used and conversions a re started by auto triggering, the adc must be switched off between conversions. when auto trig gering is used, the adc prescaler is reset before the conversion is started. since the stage i s dependent of a stable adc clock prior to the conversion, this conversion will not be valid. by d isabling and then re-enabling the adc between each conversion (writing aden in adcsra to ?0? then to ?1?), only extended conversions are performed. the result from the extended conversions will be valid. see ?prescaling and conver- sion timing? on page 275 for timing details. the gain stage is optimized for a bandwidth of 4 kh z at all gain settings. higher frequencies may be subjected to non-linear amplification. an extern al low-pass filter should be used if the input signal contains higher frequency components than th e gain stage bandwidth. note that the adc clock frequency is independent of the gain stage ba ndwidth limitation. e.g. the adc clock period may be 6 s, allowing a channel to be sampled at 12 ksps, regardless of the bandwidth of this channel. 21.5 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this e nsures that the channels and reference selection only takes place at a safe point during t he conversion. the channel and reference selection is continuously updated until a conversio n is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycl e before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is written. the user is thus advised not to wr ite new channel or reference selection values to admux until one adc clock cycle after adsc is wr itten. if auto triggering is used, the exact time of the t riggering event can be indeterministic. special care must be taken when updating the admux register , in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interr upt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: 1. when adate or aden is cleared. 2. during conversion, minimum one adc clock cycle af ter the trigger event. 3. after a conversion, before the interrupt flag use d as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. special care should be taken when changing differen tial channels. once a differential channel has been selected, the stage may take as much as 12 5 s to stabilize to the new value. thus conversions should not be started within the first 125 s after selecting a new differential chan- nel. alternatively, conversion results obtained wit hin this period should be discarded. the same settling time should be observed for the f irst differential conversion after changing adc reference (by changing the refs1:0 bits in admu x).
279 7682c?auto?04/08 at90can32/64/128 21.5.1 adc input channels when changing channel selections, the user should o bserve the following guidelines to ensure that the correct channel is selected: ? in single conversion mode, always select the chann el before starting the conversion. the channel selection may be changed one adc clock cycl e after writing one to adsc. however, the simplest method is to wait for the conversion t o complete before changing the channel selection. ? in free running mode, always select the channel be fore starting the first conversion. the channel selection may be changed one adc clock cycl e after writing one to adsc. however, the simplest method is to wait for the first conver sion to complete, and then change the channel selection. since the next conversion has al ready started automatically, the next result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. when switching to a differential gain channel, the first conversion result may have a poor accu- racy due to the required settling time for the auto matic offset cancellation circuitry. the user should preferably disregard the first conversion re sult. 21.5.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. singl e ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 2.56v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, th e external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor betw een the aref pin and ground. v ref can also be measured at the aref pin with a high impeda nt voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as th ey will be shorted to the external voltage. if no external voltage is applied to the aref pin, the us er may switch between av cc and 2.56v as reference selection. the first adc conversion resul t after switching reference voltage source may be inaccurate, and the user is advised to disca rd this result. if differential channels are used, the selected ref erence should not be closer to av cc than indi- cated in table 26-5 on page 372 . 21.6 adc noise canceler the adc features a noise canceler that enables conv ersion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals . the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion comple te interrupt must be enabled. 2. enter adc noise reduction mode (or idle mode). th e adc will start a conversion once the cpu has been halted. 3. if no other interrupts occur before the adc conve rsion completes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if
280 7682c?auto?04/08 at90can32/64/128 another interrupt wakes up the cpu before the adc c onversion is complete, that inter- rupt will be executed, and an adc conversion comple te interrupt request will be generated when the adc conversion completes. the cp u will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advi sed to write zero to aden before enter- ing such sleep modes to avoid excessive power consu mption. if the adc is enabled in such sleep modes and the u ser wants to perform differential conver- sions, the user is advised to switch the adc off an d on after waking up from sleep to prompt an extended conversion to get a valid result. 21.6.1 analog input circuitry the analog input circuitry for single ended channel s is illustrated in figure 21-8. an analog source applied to adcn is subjected to the pin capa citance and input leakage of that pin, regard- less of whether that channel is selected as input f or the adc. when the channel is selected, the source must drive the s/h capacitor through the ser ies resistance (combined resistance in the input path). the adc is optimized for analog signals with an out put impedance of approximately 10 k or less. if such a source is used, the sampling time w ill be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is re commended to only use low impedant sources with slowly varying signals, since this minimizes t he required charge transfer to the s/h capacitor. if differential gain channels are used, the input c ircuitry looks somewhat different, although source impedances of a few hundred k or less is recommended. signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredic table signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 21-8. analog input circuitry 21.6.2 analog noise canceling techniques digital circuitry inside and outside the device gen erates emi which might affect the accuracy of analog measurements. if conversion accuracy is crit ical, the noise level can be reduced by applying the following techniques: adcn i ih c s/h = 14 pf v cc /2 i il 1..100 ko
281 7682c?auto?04/08 at90can32/64/128 1. keep analog signal paths as short as possible. ma ke sure analog tracks run over the analog ground plane, and keep them well away from h igh-speed switching digital tracks. 2. the av cc pin on the device should be connected to the digit al v cc supply voltage via an lc network as shown in figure 21-9 . 3. use the adc noise canceler function to reduce ind uced noise from the cpu. 4. if any adc port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. figure 21-9. adc power connections 21.6.3 offset compensation schemes the gain stage has a built-in offset cancellation c ircuitry that nulls the offset of differential mea- surements as much as possible. the remaining offset in the analog path can be measured directly by selecting the same channel for both dif ferential inputs. this offset residue can be then subtracted in software from the measurement results . using this kind of software based offset correction, offset on any channel can be reduced be low one lsb. 21.6.4 adc accuracy definitions an n-bit single-ended adc converts a voltage linear ly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highe st code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x0 00 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. vcc gnd 100nf analog ground plane (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc3) pf3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref gnd avcc 52 53 54 55 56 57 58 59 60 61 61 62 62 63 63 64 64 1 51 nc (ad0) pa0 10uh
282 7682c?auto?04/08 at90can32/64/128 figure 21-10. offset error ? gain error: after adjusting for offset, the gain e rror is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal t ransition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 21-11. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an id eal transition for any code. ideal value: 0 lsb. output code v ref input voltage ideal adc actual ad offset error output code v ref input voltage ideal adc actual ad gain error
283 7682c?auto?04/08 at90can32/64/128 figure 21-12. integral non-linearity (inl) ? differential non-linearity (dnl): the maximum devi ation of the actual code width (the interval between two adjacent transitions) from the ideal co de width (1 lsb). ideal value: 0 lsb. figure 21-13. differential non-linearity (dnl) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an act ual (unadjusted) transition compared to an ideal transition for any code. this is the compo und effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. 21.7 adc conversion result after the conversion is complete (adif is high), th e conversion result can be found in the adc result registers (adcl, adch). output code v ref input voltage ideal adc actual ad inl output code 0x3ff 0x000 0 v ref input volta dnl 1 lsb
284 7682c?auto?04/08 at90can32/64/128 for single ended conversion, the result is: where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 21-3 on page 286 and table 21-4 on page 287 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage min us one lsb. if differential channels are used, the result is: where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor and v ref the selected voltage reference. the result is pres ented in two?s complement form, from 0x200 (-512d) throug h 0x1ff (+511d). note that if the user wants to perform a quick polarity check of the resu lt, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the result is ne gative, and if this bit is zero, the result is posi - tive. figure 21-14 shows the decoding of the differential input range . table 82 shows the resulting output codes if the di fferential input channel pair (adcn - adcm) is selected with a reference voltage of v ref . figure 21-14. differential measurement range adc v in 1023 ? v ref -------------------------- = adc v pos v neg ? ( ) gain 512 ? ? v ref --------------------------------------------------- --------------------- = 0 output code 0x1ff 0x000 v ref differential voltage (volt 0x3ff 0x200 - v ref
285 7682c?auto?04/08 at90can32/64/128 example 1: ? admux = 0xed (adc3 - adc2, 10x gain, 2.56v referen ce, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 10 * (300 - 500) / 2560 = -400 = 0x27 0 ? adcl will thus read 0x00, and adch will read 0x9c. writing zero to adlar right adjusts the result: adc l = 0x70, adch = 0x02. example 2: ? admux = 0xfb (adc3 - adc2, 1x gain, 2.56v referenc e, left adjusted result) ? voltage on adc3 is 300 mv, voltage on adc2 is 500 mv. ? adcr = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029 . ? adcl will thus read 0x40, and adch will read 0x0a. writing zero to adlar right adjusts the result: adc l = 0x00, adch = 0x29. table 21-2. correlation between input voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512
286 7682c?auto?04/08 at90can32/64/128 21.8 adc register description 21.8.1 adc multiplexer selection register ? admux ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc , as shown in table 21-3 . if these bits are changed during a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). the internal voltage refer ence options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc c onversion result in the adc data register. write one to adlar to left adjust the result. other wise, the result is right adjusted. changing the adlar bit will affect the adc data register immedia tely, regardless of any ongoing conver- sions. for a complete description of this bit, see ?the adc data register ? adcl and adch? on page 289 . ? bits 4:0 ? mux4:0: analog channel selection bits the value of these bits selects which combination o f analog inputs are connected to the adc. these bits also select the gain for the differentia l channels. see table 21-4 for details. if these bits are changed during a conversion, the change wi ll not go in effect until this conversion is complete (adif in adcsra is set). bit 7 6 5 4 3 2 1 0 refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 21-3. voltage reference selections for adc refs1 refs0 voltage reference selection 0 0 aref, internal vref turned off 0 1 av cc with external capacitor on aref pin 1 0 reserved 1 1 internal 2.56v voltage reference with external ca pacitor on aref pin
287 7682c?auto?04/08 at90can32/64/128 table 21-4. input channel and gain selections mux4..0 single ended input positive differential input negative differential input gain 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 01000 n/a (adc0 / adc0 / 10x) 01001 adc1 adc0 10x 01010 (adc0 / adc0 / 200x) 01011 adc1 adc0 200x 01100 (adc2 / adc2 / 10x) 01101 adc3 adc2 10x 01110 (adc2 / adc2 / 200x) 01111 adc3 adc2 200x 10000 adc0 adc1 1x 10001 (adc1 / adc1 / 1x) 10010 adc2 adc1 1x 10011 adc3 adc1 1x 10100 adc4 adc1 1x 10101 adc5 adc1 1x 10110 adc6 adc1 1x 10111 adc7 adc1 1x 11000 adc0 adc2 1x 11001 adc1 adc2 1x 11010 (adc2 / adc2 / 1x) 11011 adc3 adc2 1x 11100 adc4 adc2 1x 11101 adc5 adc2 1x 11110 1.1v (v band gap ) n/a 11111 0v (gnd)
288 7682c?auto?04/08 at90can32/64/128 21.8.2 adc control and status register a ? adcsra ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writing it to zero, the adc is turned off. turning the adc off while a conversion is in progress, will ter minate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion . the first conversion after adsc has been written after the adc has been enabled, or if adsc is writt en at the same time as the adc is enabled, will take 25 adc clock cycles instead of the normal 13. this first conversion performs initializa- tion of the adc. adsc will read as one as long as a conversion is in progress. when the conversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto triggering of the adc is enabled. the adc will start a con- version on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes an d the data registers are updated. the adc conversion complete interrupt is executed if th e adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corr esponding interrupt handling vector. alter- natively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify- write on adcsra, a pending interrupt can be disable d. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sr eg is set, the adc conversion complete inter- rupt is activated. bit 7 6 5 4 3 2 1 0 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
289 7682c?auto?04/08 at90can32/64/128 ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between th e xtal frequency and the input clock to the adc. 21.8.3 the adc data register ? adcl and adch adlar = 0 adlar = 1 when an adc conversion is complete, the result is f ound in these two registers. if differential channels are used, the result is presented in two?s complement form. when adcl is read, the adc data register is not upd ated until adch is read. consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read adc h. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is cleared (default), the result is right adjusted. table 21-5. adc prescaler selections adps2 adps1 adps0 division factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 bit 15 14 13 12 11 10 9 8 ? ? ? ? ? ? adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl bit 7 6 5 4 3 2 1 0 read/write r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 ? ? ? ? ? ? adcl bit 7 6 5 4 3 2 1 0 read/write r r r r r r r r r r r r r r r r initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
290 7682c?auto?04/08 at90can32/64/128 ? adc9:0: adc conversion result these bits represent the result from the conversion , as detailed in ?adc conversion result? on page 283 . 21.8.4 adc control and status register b ? adcsrb ? bit 7? reserved bit this bit is reserved for future use. for compatibil ity with future devices, it must be written to zero when adcsrb is written. ? bit 5:3? reserved bits these bits are reserved for future use. for compati bility with future devices, they must be written to zero when adcsrb is written. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the rising edge of the selecte d interrupt flag. note that switching from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if the adc interrupt flag is set . bit 7 6 5 4 3 2 1 0 ? acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 21-6. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event
291 7682c?auto?04/08 at90can32/64/128 21.8.5 digital input disable register 0 ? didr0 ? bit 7:0 ? adc7d..adc0d: adc7:0 digital input disab le when this bit is written logic one, the digital inp ut buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will alwa ys read as zero when this bit is set. when an analog signal is applied to the adc7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power con sumption in the digital input buffer. bit 7 6 5 4 3 2 1 0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
292 7682c?auto?04/08 at90can32/64/128 22. jtag interface and on-chip debug system 22.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the ieee st d. 1149.1 (jtag) standard ? debugger access to: ? all internal peripheral units ? internal and external ram ? the internal register file ? program counter ? eeprom and flash memories ? extensive on-chip debug support for break condition s, including ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on single address or a ddress range ? data memory break points on single address or addr ess range ? programming of flash, eeprom, fuses, and lock bits through the jtag interface ? on-chip debugging supported by avr studio ? 22.2 overview the avr ieee std. 1149.1 compliant jtag interface c an be used for: ? testing pcbs by using the jtag boundary-scan capab ility ? programming the non-volatile memories, fuses and l ock bits ? on-chip debugging a brief description is given in the following secti ons. detailed descriptions for programming via the jtag interface, and using the boundary-scan cha in can be found in the sections ?jtag programming overview? on page 351 and ?boundary-scan ieee 1149.1 (jtag)? on page 299 , respectively. the on-chip debug support is consider ed being private jtag instructions, and dis- tributed within atmel and to selected third party v endors only. figure 22-1 shows a block diagram of the jtag interface and th e on-chip debug system. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift register) between the tdi ? input and tdo ? output. the instruction register holds jtag instructions controlling the behavior of a data reg ister. the id-register (identifier register), bypass regis ter, and the boundary-scan chain are the data registers used for board-level testing. the jt ag programming interface (actually consist- ing of several physical and virtual data registers) is used for serial programming via the jtag interface. the internal scan chain and break point scan chain are used for on-chip debugging only. 22.3 test access port ? tap the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test access port ? tap. these pins a re: ? tms : test mode select. this pin is used for navigating through the tap-controller state machine.
293 7682c?auto?04/08 at90can32/64/128 ? tck : test clock. jtag operation is synchronous to tck. ? tdi : test data in. serial input data to be shifted in to the instruction register or data register (scan chains). ? tdo : test data out. serial output data from instructio n register or data register (scan chains). the ieee std. 1149.1 also specifies an optional tap signal; trst ? test reset ? which is not provided. when the jtagen fuse is unprogrammed, these four ta p pins are normal port pins and the tap controller is in reset. when programmed and the jtd bit in mcucr is cleared, the tap input signals are internally pulled high and the jt ag is enabled for boundary-scan and program- ming. in this case, the tap output pin (tdo) is lef t floating in states where the jtag tap controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the tdi-inpu t of the next device in the scan chain). the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jt ag interface pins, the reset pin is moni- tored by the debugger to be able to detect external reset sources. the debugger can also pull the reset pin low to reset the whole system, assuming only o pen collectors on the reset line are used in the application.
294 7682c?auto?04/08 at90can32/64/128 figure 22-1. block diagram tap controller tdi tdo tck tms flash memory avr cpu digital peripheral units jtag / avr core communication interface breakpoint unit flow control unit ocd status and control internal scan chain m u x instruction register id register bypass register jtag programming interface pc instruction address data breakpoint scan chain address decoder analog peripherial units i/o port 0 i/o port n boundary scan chain analog inputs control & clock lines device boundary
295 7682c?auto?04/08 at90can32/64/128 figure 22-2. tap controller state diagram 22.4 tap controller the tap controller is a 16-state finite state machi ne that controls the operation of the boundary- scan circuitry, jtag programming circuitry, or on-c hip debug system. the state transitions depicted in figure 22-2 depend on the signal present on tms (shown adjacen t to each state transition) at the time of the rising edge at tck. the initial state after a power-on reset is test- logic-reset. as a definition in this document, the lsb is shifte d in and out first for all shift registers. assuming run-test/idle is the present state, a typi cal scenario for using the jtag interface is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? shift-ir state. while in thi s state, shift the four bits of the jtag instructions into the jtag instruction register fro m the tdi input at the rising edge of tck. the tms input must be held low during input of the 3 lsbs in order to remain in the shift-ir state. the msb of the instruction is shifted in whe n this state is left by setting tms high. while the instruction is shifted in from the tdi pi n, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a particu lar data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. t est-logic-reset run-t est/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1
296 7682c?auto?04/08 at90can32/64/128 ? apply the tms sequence 1, 1, 0 to re-enter the run -test/idle state. the instruction is latched onto the parallel output from the shift register pa th in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for nav igating the state machine. ? at the tms input, apply the sequence 1, 0, 0 at th e rising edges of tck to enter the shift data register ? shift-dr state. while in this state , upload the selected data register (selected by the present jtag instruction in the jtag instruc tion register) from the tdi input at the rising edge of tck. in order to remain in the shift -dr state, the tms input must be held low during input of all bits except the msb. the msb of the data is shifted in when this state is left by setting tms high. while the data register is shi fted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr sta te is shifted out on the tdo pin. ? apply the tms sequence 1, 1, 0 to re-enter the run -test/idle state. if the selected data register has a latched parallel-output, the latchin g takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states are only use d for navigating the state machine. as shown in the state diagram, the run-test/idle st ate need not be entered between selecting jtag instruction and using data registers, and some jtag instructions may select certain func- tions to be performed in the run-test/idle, making it unsuitable as an idle state. note: independent of the initial state of the tap co ntroller, the test-logic-reset state can always be entered by holding tms high for five tck clock peri ods. for detailed information on the jtag specification, refer to the literature listed in ?bibliography? on page 298 . 22.5 using the boundary-scan chain a complete description of the boundary-scan capabil ities are given in the section ?boundary- scan ieee 1149.1 (jtag)? on page 299 . 22.6 using the on-chip debug system as shown in figure 22-1 , the hardware support for on-chip debugging consis ts mainly of ? a scan chain on the interface between the internal avr cpu and the internal peripheral units. ? break point unit. ? communication interface between the cpu and jtag s ystem. all read or modify/write operations needed for impl ementing the debugger are done by applying avr instructions via the internal avr cpu scan chai n. the cpu sends the result to an i/o memory mapped location which is part of the communi cation interface between the cpu and the jtag system. the break point unit implements break on change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: ? 4 single program memory break points. ? 3 single program memory break points + 1 single da ta memory break point. ? 2 single program memory break points + 2 single da ta memory break points.
297 7682c?auto?04/08 at90can32/64/128 ? 2 single program memory break points + 1 program m emory break point with mask (?range break point?). ? 2 single program memory break points + 1 data memo ry break point with mask (?range break point?). a debugger, like the avr studio, may however use on e or more of these resources for its inter- nal purpose, leaving less flexibility to the end-us er. a list of the on-chip debug specific jtag instructi ons is given in ?on-chip debug specific jtag instructions? on page 297 . the jtagen fuse must be programmed to enable the jt ag test access port. in addition, the ocden fuse must be programmed and no lock bits must be set for the on-chip debug system to work. as a security feature, the on-chip debug s ystem is disabled when either of the lb1 or lb2 lock bits are set. otherwise, the on-chip debug system would have provided a back-door into a secured device. the avr studio enables the user to fully control ex ecution of programs on an avr device with on-chip debug capability, avr in-circuit emulator, or the built-in avr instruction set simulator. avr studio ? supports source level execution of assembly progra ms assembled with atmel cor- poration?s avr assembler and c programs compiled wi th third party vendors? compilers. avr studio runs under microsoft ? windows ? 95/98/2000/nt/xp. for a full description of the avr studio, please re fer to the avr studio user guide. only high- lights are presented in this document. all necessary execution commands are available in a vr studio, both on source level and on disassembly level. the user can execute the program , single step through the code either by tracing into or stepping over functions, step out o f functions, place the cursor on a statement and execute until the statement is reached, stop the ex ecution, and reset the execution target. in addition, the user can have an unlimited number of code break points (using the break instruction) and up to two data memory break points , alternatively combined as a mask (range) break point. 22.7 on-chip debug specific jtag instructions the on-chip debug support is considered being priva te jtag instructions, and distributed within atmel and to selected third party vendors only. ins truction opcodes are listed for reference. 22.7.1 private0 (0x8) private jtag instruction for accessing on-chip debu g system. 22.7.2 private1 (0x9) private jtag instruction for accessing on-chip debu g system. 22.7.3 private2 (0xa) private jtag instruction for accessing on-chip debu g system. 22.7.4 private3 (0xb) private jtag instruction for accessing on-chip debu g system.
298 7682c?auto?04/08 at90can32/64/128 22.8 on-chip debug related register in i/o memory 22.8.1 on-chip debug register ? ocdr the ocdr register provides a communication channel from the running program in the micro- controller to the debugger. the cpu can transfer a byte to the debugger by writing to this location. at the same time, an internal flag; i/o d ebug register dirty ? idrd ? is set to indicate to the debugger that the register has been written. when the cpu reads the ocdr register the 7 lsb will be from the ocdr register, while the msb is the idrd bit. the debugger clears the idrd bit when it has read the information. in some avr devices, this register is shared with a standard i/o location. in this case, the ocdr register can only be accessed if the ocden fuse is programmed, and the debugger enables access to the ocdr register. in all other cases, th e standard i/o location is accessed. refer to the debugger documentation for further inf ormation on how to use this register. 22.9 using the jtag programming capabilities programming of avr parts via jtag is performed via the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins that need to be contro lled/observed to perform jtag program- ming (in addition to power pins). it is not require d to apply 12v externally. the jtagen fuse must be programmed and the jtd bit in the mcucr reg ister must be cleared to enable the jtag test access port. the jtag programming capability supports: ? flash programming and verifying. ? eeprom programming and verifying. ? fuse programming and verifying. ? lock bit programming and verifying. the lock bit security is exactly as in parallel pro gramming mode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be programmed unl ess first doing a chip erase. this is a security feature that ensures no back-door exists f or reading out the content of a secured device. the details on programming through the jtag interfa ce and programming specific jtag instructions are given in the section ?jtag programming overview? on page 351 . 22.10 bibliography for more information about general boundary-scan, t he following literature can be consulted: ? ieee: ieee std 1149.1-1990. ieee standard test acc ess port and boundary-scan architecture, ieee, 1993. ? colin maunder: the board designers guide to testab le logic circuits, addison-wesley, 1992. bit 7 6 5 4 3 2 1 0 idrd/ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 ocdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
299 7682c?auto?04/08 at90can32/64/128 23. boundary-scan ieee 1149.1 (jtag) 23.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities according to the jtag st andard ? full scan of all port functions as well as analog c ircuitry having off-chip connections ? supports the optional idcode instruction ? additional public avr_reset instruction to reset th e avr 23.2 system overview the boundary-scan chain has the capability of drivi ng and observing the logic levels on the digi- tal i/o pins, as well as the boundary between digit al and analog logic for analog circuitry having off-chip connections. at system level, all ics havi ng jtag capabilities are connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. the controller compares the received data with the expe cted result. in this way, boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag instruc tions idcode, bypass, sample/pre- load, and extest, as well as the avr specific publi c jtag instruction avr_reset can be used for testing the printed circuit board. initial scanning of the data register path will show the id-code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if n ot reset, inputs to the device may be deter- mined by the scan operations, and the internal soft ware may be in an undetermined state when exiting the test mode. entering reset, the outputs of any port pin will instantly enter the high impedance state, making the highz instruction redun dant. if needed, the bypass instruction can be issued to make the shortest possible scan ch ain through the device. the device can be set in the reset state either by pulling the extern al reset pin low, or issuing the avr_reset instruction with appropriate setting of the reset d ata register. the extest instruction is used for sampling externa l pins and loading output pins with data. the data from the output latch will be driven out o n the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial values to the scan ring, to avoid d amaging the board when issuing the extest instruction for the first time. sample/preload can also be used for taking a snapshot of the external pins during normal operation of the part. the jtagen fuse must be programmed and the jtd bit in the i/o register mcucr must be cleared to enable the jtag test access port. when using the jtag interface for boundary-scan, us ing a jtag tck clock frequency higher than the internal chip frequency is possible. the c hip clock is not required to run. 23.3 data registers the data registers relevant for boundary-scan opera tions are: ? bypass register ? device identification register ? reset register ? boundary-scan chain
300 7682c?auto?04/08 at90can32/64/128 23.3.1 bypass register the bypass register consists of a single shift regi ster stage. when the bypass register is selected as path between tdi and tdo, the register is reset to 0 when leaving the capture-dr controller state. the bypass register may be used t o shorten the scan chain on a system when the other devices are to be tested. 23.3.2 device identification register figure 23-1 shows the structure of the device identification r egister. figure 23-1. the format of the device identification register 23.3.2.1 version version is a 4-bit number identifying the revision of the component. the relevant version number is shown in table 23-1 . 23.3.2.2 part number the part number is a 16-bit code identifying the co mponent. the jtag part number for at90can32/64/128 is listed in table 23-2 . 23.3.2.3 manufacturer id the manufacturer id is a 11-bit code identifying th e manufacturer. the jtag manufacturer id for atmel is listed in table 23-3 . msb lsb bit 31 28 27 12 11 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit table 23-1. jtag version numbers version jtag version number (hex) at90can32 revisionb 0x0 at90can64 revision a 0x0 at90can128 revision d 0x0 table 23-2. avr jtag part number part number jtag part number (hex) at90can32 0x9581 at90can64 0x9681 at90can128 0x9781 table 23-3. manufacturer id manufacturer jtag manufacturer id (hex) atmel 0x01f
301 7682c?auto?04/08 at90can32/64/128 23.3.2.4 device id the full device id is listed in table 23-4 following the at90can32/64/128 version. 23.3.3 reset register the reset register is a test data register used to reset the part. since the avr tri-states port pins when reset, the reset register can also replac e the function of the unimplemented optional jtag instruction highz. a high value in the reset register corresponds to p ulling the external reset low. the part is reset as long as there is a high value present in t he reset register. depending on the fuse set- tings for the clock options, the part will remain r eset for a reset time-out period (refer to ?system clock? on page 37 ) after releasing the reset register. the output fr om this data register is not latched, so the reset will take place immediately, as shown in figure 23-2 . figure 23-2. reset register 23.3.4 boundary-scan chain the boundary-scan chain has the capability of drivi ng and observing the logic levels on the dig- ital i/o pins, as well as the boundary between digi tal and analog logic for analog circuitry having off-chip connections. see ?boundary-scan chain? on page 303 for a complete description. 23.4 boundary-scan specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. listed below are the jtag instructions useful for boundary-scan operation. no te that the optional highz instruction is not implemented, but all outputs with tri-state capabil ity can be set in high-impedant state by using the avr_reset instruction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shift ed in and out first for all shift registers. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path b etween tdi and tdo for each instruction. table 23-4. device id version jtag device id (hex) at90can32 revision b 0x0958103f at90can64 revision a 0x0968103f at90can128 revision d 0x0978103f d q from tdi clockdr avr_reset to tdo from other internal and external reset sources internal reset
302 7682c?auto?04/08 at90can32/64/128 23.4.1 extest (0x0) mandatory jtag instruction for selecting the bounda ry-scan chain as data register for testing circuitry external to the avr package. for port-pin s, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog circuits having off-chip connections, the interface between the analog and t he digital logic is in the scan chain. the con- tents of the latched outputs of the boundary-scan c hain is driven out as soon as the jtag ir- register is loaded with the extest instruction. the active states are: ? capture-dr : data on the external pins are sampled into the bo undary-scan chain. ? shift-dr : the internal scan chain is shifted by the tck inp ut. ? update-dr : data from the scan chain is applied to output pin s. 23.4.2 idcode (0x1) optional jtag instruction selecting the 32 bit id-r egister as data register. the id-register con- sists of a version number, a device number and the manufacturer code chosen by jedec. this is the default instruction after power-up. the active states are: ? capture-dr : data in the idcode register is sampled into the b oundary-scan chain. ? shift-dr : the idcode scan chain is shifted by the tck input . 23.4.3 sample_preload (0x2) mandatory jtag instruction for pre-loading the outp ut latches and taking a snap-shot of the input/output pins without affecting the system oper ation. however, the output latches are not connected to the pins. the boundary-scan chain is s elected as data register. the active states are: ? capture-dr : data on the external pins are sampled into the bo undary-scan chain. ? shift-dr : the boundary-scan chain is shifted by the tck inp ut. ? update-dr : data from the boundary-scan chain is applied to t he output latches. however, the output latches are not connected to the pins. 23.4.4 avr_reset (0xc) the avr specific public jtag instruction for forcin g the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this instruction. the one bit reset register is selected as data register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: ? shift-dr : the reset register is shifted by the tck input. 23.4.5 bypass (0xf) mandatory jtag instruction selecting the bypass reg ister for data register. the active states are: ? capture-dr : loads a logic ?0? into the bypass register.
303 7682c?auto?04/08 at90can32/64/128 ? shift-dr : the bypass register cell between tdi and tdo is s hifted. 23.5 boundary-scan related register in i/o memory 23.5.1 mcu control register ? mcucr the mcu control register contains control bits for general mcu functions. ? bits 7 ? jtd: jtag interface disable when this bit is zero, the jtag interface is enable d if the jtagen fuse is programmed. if this bit is one, the jtag interface is disabled. in orde r to avoid unintentional disabling or enabling of the jtag interface, a timed sequence must be follow ed when changing this bit: the application software must write this bit to the desired value t wice within four cycles to change its value. note that this bit must not be altered when using the on -chip debug system. if the jtag interface is left unconnected to other jtag circuitry, the jtd bit should be set to one. the reason for this is to avoid static current at the tdo pin in the jtag interface. 23.5.2 mcu status register ? mcusr the mcu status register provides information on whi ch reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a log ic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is reset b y a power-on reset, or by writing a logic zero to the flag. 23.6 boundary-scan chain the boundary-scan chain has the capability of drivi ng and observing the logic levels on the digi- tal i/o pins, as well as the boundary between digit al and analog logic for analog circuitry having off-chip connection. 23.6.1 scanning the digital port pins figure 23-3 shows the boundary-scan cell for a bi-directional port pin with pull-up function. the cell consists of a standard boundary-scan cell for the pull-up enable ? puexn ? function, and a bi-directional pin cell that combines the three sig nals output control ? ocxn, output data ? odxn, and input data ? idxn, into only a two-stage shift register. the port and pin indexes are not used in the following description the boundary-scan logic is not included in the figu res in the datasheet. figure 23-4 shows a simple digital port pin as described in the section ?i/o-ports? on page 66 . the boundary-scan details from figure 23-3 replaces the dashed box in figure 23-4 . bit 7 6 5 4 3 2 1 0 jtd ? ? pud ? ? ivsel ivce mcucr read/write r/w r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 ? ? ? jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description
304 7682c?auto?04/08 at90can32/64/128 when no alternate port function is present, the inp ut data ? id ? corresponds to the pinxn reg- ister value (but id has no synchronizer), output da ta corresponds to the port register, output control corresponds to the data direction ? dd regi ster, and the pull-up enable ? puexn ? cor- responds to logic expression pud ddxn portxn. digital alternate port functions are connected outs ide the dotted box in figure 23-4 to make the scan chain read the actual pin value. for analog fu nction, there is a direct connection from the external pin to the analog circuit, and a scan chai n is inserted on the interface between the digi- tal logic and the analog circuitry. figure 23-3. boundary-scan cell for bi-directional port pin with pull-up function. d q d q g 0 1 0 1 d q d q g 0 1 0 1 0 1 0 1 d q d q g 0 1 port pin (pxn) vcc extest to next cell shiftdr output control (oc) pullup enable (pue) output data (od) input data (id) from last cell updatedr clockdr ff2 ld2 ff1 ld1 ld0 ff0
305 7682c?auto?04/08 at90can32/64/128 figure 23-4. general port pin schematic diagram 23.6.2 boundary-scan and the two-wire interface the two two-wire interface pins scl and sda have on e additional control signal in the scan- chain; two-wire interface enable ? twien. as shown in figure 23-5 , the twien signal enables a tri-state buffer with slew-rate control in parall el with the ordinary digital port pins. a general scan cell as shown in figure 23-9 is attached to the twien signal. notes: 1. a separate scan chain for the 50 ns spike f ilter on the input is not provided. the ordinary sc an support for digital port pins suffice for connectiv ity tests. the only reason for having twien in the scan path, is to be able to disconnect the slew -rate control buffer when doing boundary- scan. 2. make sure the oc and twien signals are not assert ed simultaneously, as this will lead to drive contention. clk rpx rrx wpx rdx wdx pud synchronizer wdx: write ddrx wpx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk :i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data bus sleep sleep: sleep control pxn i/o i/o see boundary-scan description for details! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output data to pin pxn idxn: input data from pin pxn
306 7682c?auto?04/08 at90can32/64/128 figure 23-5. additional scan signal for the two-wire interface 23.6.3 scanning the reset pin the reset pin accepts 3v or 5v active low logic for standard reset operation, and 12v active high logic for high voltage parallel programming. a n observe-only cell as shown in figure 23-6 is inserted both for the 3v or 5v reset signal - rs tt, and the 12v reset signal - rsthv. figure 23-6. observe-only cell for reset pin 23.6.4 scanning the clock pins the avr devices have many clock options selectable by fuses. these are: internal rc oscilla- tor, external clock, (high frequency) crystal oscil lator, low-frequency crystal oscillator, and ceramic resonator. figure 23-7 shows how each oscillator with external connection is supported in the scan chain. the enable signal is supported with a general bound ary-scan cell, while the oscillator/clock out- put is attached to an observe-only cell. in additio n to the main clock, the timer2 oscillator is scanned in the same way. the output from the intern al rc oscillator is not scanned, as this oscillator does not have external connections. pxn puexn odxn idxn twien ocxn slew-rate limited src 0 1 d q from previous cell clockdr shiftdr to next cell from system pin to system logic ff1
307 7682c?auto?04/08 at90can32/64/128 figure 23-7. boundary-scan cells for oscillators and clock optio ns table 23-5 summaries the scan registers for the external cloc k pin xtal1, oscillators with xtal1/xtal2 connections as well as external timer2 clock pin tosc1 and 32khz timer2 oscillator. notes: 1. do not enable more than one clock source as clock at a time. 2. scanning an oscillator output gives unpredictable results as there is a frequency drift between the internal oscillator and the jtag tck clock. if possible, scanning an external clock is preferred. 3. the main clock configuration is programmed by fus es. as a fuse is not changed run-time, the main clock configuration is considered fixed for a given application. the user is advised to scan the same clock option as to be used in the fin al system. the enable signals are sup- ported in the scan chain because the system logic c an disable clock options in sleep modes, thereby disconnecting the oscillator pins from the scan path if not provided. 23.6.5 scanning the analog comparator the relevant comparator signals regarding boundary- scan are shown in figure 23-8 . the boundary-scan cell from figure 23-9 is attached to each of these signals. the signals are described in table 23-6 . the comparator need not be used for pure connectivi ty testing, since all analog inputs are shared with a digital port pin as well. table 23-5. scan signals for the oscillators (1)(2)(3) enable signal scanned clock line clock option scanned clock line when not used extclken extclk (xtal1) external main clock 0 oscon oscck external crystal external ceramic resonator 1 osc32en osc32ck low freq. external crystal 1 toskon tosck 32 khz timer2 oscillator 1 0 1 d q from previous cell clockdr shiftdr to next cell to system logic ff1 0 1 d q d q g 0 1 from previous cell clockdr updatedr shiftdr to next cell extest from digital logic xtal1 / tosc1 xtal2 / tosc2 oscillator enable output
308 7682c?auto?04/08 at90can32/64/128 figure 23-8. analog comparator figure 23-9. general boundary-scan cell used for signals for com parator and adc table 23-6. boundary-scan signals for the analog comparator signal name direction as seen from the comparator description recommended input when not in use output values when recommended inputs are used ac_idle input turns off analog comparator when true 1 depends upon c code being executed aco output analog comparator output will become input to c code being executed 0 acme input uses output signal from adc mux when true 0 depends upon c code being executed acbg input bandgap reference enable 0 depends upon c code being executed acbg bandgap reference adc multiplexer output acme ac_idle aco adcen 0 1 d q d q g 0 1 from previous cell clockdr updatedr shiftdr to next cell extest to analog circuitry/ to digital logic from digital logic/ from analog ciruitry
309 7682c?auto?04/08 at90can32/64/128 23.6.6 scanning the adc figure 23-10 shows a block diagram of the adc with all relevant control and observe signals. the boundary-scan cell from figure 23-9 is attached to each of these signals. the adc need not be used for pure connectivity testing, since al l analog inputs are shared with a digital port pin as well. figure 23-10. analog to digital converter the signals are described briefly in table 23-7 . + - aref prech dacout comp muxen_7 adc_7 muxen_6 adc_6 muxen_5 adc_5 muxen_4 adc_4 muxen_3 adc_3 muxen_2 adc_2 muxen_1 adc_1 muxen_0 adc_0 negsel_2 adc_2 negsel_1 adc_1 negsel_0 adc_0 extch + - + - 10x 20x 10-bit dac st aclk ampen 2.56v ref irefen aref vccren dac_9..0 adcen hold prech gnden passen acten comp sctest adcbgen t o comparator g20 g10 1.22v ref
310 7682c?auto?04/08 at90can32/64/128 table 23-7. boundary-scan signals for the adc (1) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc comp output comparator output 0 0 aclk input clock signal to gain stages implemented as switch-cap filters 0 0 acten input enable path from gain stages to the comparator 0 0 adcbgen input enable band-gap reference as negative input to comparator 0 0 adcen input power-on signal to the adc 0 0 ampen input power-on signal to the gain stages 0 0 dac_9 input bit 9 of digital value to dac 1 1 dac_8 input bit 8 of digital value to dac 0 0 dac_7 input bit 7 of digital value to dac 0 0 dac_6 input bit 6 of digital value to dac 0 0 dac_5 input bit 5 of digital value to dac 0 0 dac_4 input bit 4 of digital value to dac 0 0 dac_3 input bit 3 of digital value to dac 0 0 dac_2 input bit 2 of digital value to dac 0 0 dac_1 input bit 1 of digital value to dac 0 0 dac_0 input bit 0 of digital value to dac 0 0 extch input connect adc channels 0 - 3 to by-pass path around gain stages 1 1 g10 input enable 10x gain 0 0 g20 input enable 20x gain 0 0
311 7682c?auto?04/08 at90can32/64/128 gnden input ground the negative input to comparator when true 0 0 hold input sample & hold signal. sample analog signal when low. hold signal when high. if gain stages are used, this signal must go active when aclk is high. 1 1 irefen input enables band-gap reference as aref signal to dac 0 0 muxen_7 input input mux bit 7 0 0 muxen_6 input input mux bit 6 0 0 muxen_5 input input mux bit 5 0 0 muxen_4 input input mux bit 4 0 0 muxen_3 input input mux bit 3 0 0 muxen_2 input input mux bit 2 0 0 muxen_1 input input mux bit 1 0 0 muxen_0 input input mux bit 0 1 1 negsel_2 input input mux for negative input for differential signal, bit 2 0 0 negsel_1 input input mux for negative input for differential signal, bit 1 0 0 negsel_0 input input mux for negative input for differential signal, bit 0 0 0 passen input enable pass-gate of gain stages. 1 1 prech input precharge output latch of comparator. (active low) 1 1 table 23-7. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc
312 7682c?auto?04/08 at90can32/64/128 note: 1. incorrect setting of the switches in figure 23-10 will make signal contention and may damage the part. there are several input choices to the s& h circuitry on the negative input of the out- put comparator in figure 23-10 . make sure only one path is selected from either o ne adc pin, bandgap reference source, or ground. if the adc is not to be used during scan, the recom mended input values from table 23-7 should be used. the user is recommended not to use the differential gain stages during scan. s witch- cap based gain stages require fast operation and ac curate timing which is difficult to obtain when used in a scan chain. details concerning opera tions of the differential gain stage is there- fore not provided. the avr adc is based on the analog circuitry shown in figure 23-10 with a successive approx- imation algorithm implemented in the digital logic. when used in boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. this can easily be done without running a successive approximation algorithm: apply the lower limit on the digi- tal dac[9:0] lines, make sure the output from the c omparator is low, then apply the upper limit on the digital dac[9:0] lines, and verify the outpu t from the comparator to be high. the adc need not be used for pure connectivity test ing, since all analog inputs are shared with a digital port pin as well. when using the adc, remember the following ? the port pin for the adc channel in use must be co nfigured to be an input with pull-up disabled to avoid signal contention. ? in normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the adc. the user is advised to wait at le ast 200ns after enabling the adc before controlling/observing any adc signal, or perform a dummy conversion before using the first result. ? the dac values must be stable at the midpoint valu e 0x200 when having the hold signal low (sample mode). as an example, consider the task of verifying a 1.5 v 5% input signal at adc channel 3 when the power supply is 5.0v and aref is externally con nected to v cc. sctest input switch-cap test enable. output from x10 gain stage send out to port pin having adc_4 0 0 st input output of gain stages will settle faster if this signal is high first two aclk periods after ampen goes high. 0 0 vccren input selects vcc as the acc reference voltage. 0 0 the lower limit is: [ 1024 * 1.5v * 0.95 / 5v ] = 291 = 0x123 the upper limit is: [ 1024 * 1.5v * 1.05 / 5v ] = 323 = 0x143 table 23-7. boundary-scan signals for the adc (1) (continued) signal name direction as seen from the adc description recommended input when not in use output values when recommended inputs are used, and cpu is not using the adc
313 7682c?auto?04/08 at90can32/64/128 the recommended values from table 23-7 are used unless other values are given in the algo - rithm in table 23-8 . only the dac and port pin values of the scan chai n are shown. the column ?actions? describes what jtag instruction to be use d before filling the boundary-scan register with the succeeding columns. the verification shoul d be done on the data scanned out when scanning in the data on the same row in the table. using this algorithm, the timing constraint on the hold signal constrains the tck clock fre- quency. as the algorithm keeps hold high for five s teps, the tck clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, t hold,max 23.7 at90can32/64/128 boundary-scan order table 23-9 shows the scan order between tdi and tdo when the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follows the pin-out order as far as poss ible. therefore, the bits of port a is scanned in the opposite bit order of the other ports. exceptio ns from the rules are the scan chains for the analog circuits, which constitute the most signific ant bits of the scan chain regardless of which physical pin they are connected to. in figure 23-3 , pxn. data corresponds to ff0, pxn. control table 23-8. algorithm for using the adc step actions adcen dac muxen hold prech pa3. data pa3. control pa3. pullup_ enable 1 sample_ preload 1 0x200 0x08 1 1 0 0 0 2 extest 1 0x200 0x08 0 1 0 0 0 3 1 0x200 0x08 1 1 0 0 0 4 1 0x123 0x08 1 1 0 0 0 5 1 0x123 0x08 1 0 0 0 0 6 verify the comp bit scanned out to be 0 1 0x200 0x08 1 1 0 0 0 7 1 0x200 0x08 0 1 0 0 0 8 1 0x200 0x08 1 1 0 0 0 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 11 verify the comp bit scanned out to be 1 1 0x200 0x08 1 1 0 0 0
314 7682c?auto?04/08 at90can32/64/128 corresponds to ff1, and pxn. pullup_enable correspo nds to ff2. bit 2, 3, 4, and 5 of port c is not in the scan chain, since these pins constitute the tap pins when the jtag is enabled. table 23-9. at90can32/64/128 boundary-scan order bit number signal name comment module 200 ac_idle comparator 199 aco 198 acme 197 ainbg 196 comp adc 195 aclk 194 acten 193 private_signal (1) 192 adcbgen 191 adcen 190 ampen 189 dac_9 188 dac_8 187 dac_7 186 dac_6 185 dac_5 184 dac_4 183 dac_3 182 dac_2 181 dac_1 180 dac_0 179 extch 178 g10 177 g20 176 gnden 175 hold 174 irefen 173 muxen_7 172 muxen_6 171 muxen_5 170 muxen_4 169 muxen_3 168 muxen_2 167 muxen_1 166 muxen_0 165 negsel_2
315 7682c?auto?04/08 at90can32/64/128 164 negsel_1 adc 163 negsel_0 162 passen 161 prech 160 sctest 159 st 158 vccren 157 pe0.data port e 156 pe0.control 155 pe0.pullup_enable 154 pe1.data 153 pe1.control 152 pe1.pullup_enable 151 pe2.data 150 pe2.control 149 pe2.pullup_enable 148 pe3.data 147 pe3.control 146 pe3.pullup_enable 145 pe4.data 144 pe4.control 143 pe4.pullup_enable 142 pe5.data 141 pe5.control 140 pe5.pullup_enable 139 pe6.data 138 pe6.control 137 pe6.pullup_enable 136 pe7.data 135 pe7.control 134 pe7.pullup_enable 133 pb0.data port b 132 pb0.control 131 pb0.pullup_enable 130 pb1.data 129 pb1.control 128 pb1.pullup_enable 127 pb2.data table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module
316 7682c?auto?04/08 at90can32/64/128 126 pb2.control port b 125 pb2.pullup_enable 124 pb3.data 123 pb3.control 122 pb3.pullup_enable 121 pb4.data 120 pb4.control 119 pb4.pullup_enable 118 pb5.data 117 pb5.control 116 pb5.pullup_enable 115 pb6.data 114 pb6.control 113 pb6.pullup_enable 112 pb7.data 111 pb7.control 110 pb7.pullup_enable 109 pg3.data port g 108 pg3.control 107 pg3.pullup_enable 106 pg4.data 105 pg4.control 104 pg4.pullup_enable 103 private_signal (1) ? 102 rstt (observe only) reset logic 101 rsthv 100 extclken oscillators 99 oscon 98 osc32en 97 toskon 96 extclk (xtal1) 95 oscck 94 osc32ck 93 tosk 92 pd0.data port d 91 pd0.control 90 pd0.pullup_enable 89 pd1.data table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module
317 7682c?auto?04/08 at90can32/64/128 88 pd1.control port d 87 pd1.pullup_enable 86 pd2.data 85 pd2.control 84 pd2.pullup_enable 83 pd3.data 82 pd3.control 81 pd3.pullup_enable 80 pd4.data 79 pd4.control 78 pd4.pullup_enable 77 pd5.data 76 pd5.control 75 pd5.pullup_enable 74 pd6.data 73 pd6.control 72 pd6.pullup_enable 71 pd7.data 70 pd7.control 69 pd7.pullup_enable 68 pg0.data port g 67 pg0.control 66 pg0.pullup_enable 65 pg1.data 64 pg1.control 63 pg1.pullup_enable 62 pc0.data port c 61 pc0.control 60 pc0.pullup_enable 59 pc1.data 58 pc1.control 57 pc1.pullup_enable 56 pc2.data 55 pc2.control 54 pc2.pullup_enable 53 pc3.data 52 pc3.control 51 pc3.pullup_enable table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module
318 7682c?auto?04/08 at90can32/64/128 50 pc4.data port c 49 pc4.control 48 pc4.pullup_enable 47 pc5.data 46 pc5.control 45 pc5.pullup_enable 44 pc6.data 43 pc6.control 42 pc6.pullup_enable 41 pc7.data 40 pc7.control 39 pc7.pullup_enable 38 pg2.data port g 37 pg2.control 36 pg2.pullup_enable 35 pa7.data port a 34 pa7.control 33 pa7.pullup_enable 32 pa6.data 31 pa6.control 30 pa6.pullup_enable 29 pa5.data 28 pa5.control 27 pa5.pullup_enable 26 pa4.data 25 pa4.control 24 pa4.pullup_enable 23 pa3.data 22 pa3.control 21 pa3.pullup_enable 20 pa2.data 19 pa2.control 18 pa2.pullup_enable 17 pa1.data 16 pa1.control 15 pa1.pullup_enable 14 pa0.data 13 pa0.control table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module
319 7682c?auto?04/08 at90can32/64/128 notes: 1. private_signal should always be scanned-in as zero. 23.8 boundary-scan description language files boundary-scan description language (bsdl) files des cribe boundary-scan capable devices in a standard format used by automated test-generation software. the order and function of bits in the boundary-scan data register are included in thi s description. a bsdl file for at90can32/64/128 is available. 12 pa0.pullup_enable port a 11 pf3.data port f 10 pf3.control 9 pf3.pullup_enable 8 pf2.data 7 pf2.control 6 pf2.pullup_enable 5 pf1.data 4 pf1.control 3 pf1.pullup_enable 2 pf0.data 1 pf0.control 0 pf0.pullup_enable table 23-9. at90can32/64/128 boundary-scan order (continued) bit number signal name comment module
320 7682c?auto?04/08 at90can32/64/128 24. boot loader support ? read-while-write self-prog ramming the boot loader support provides a real read-while- write self-programming mechanism for downloading and uploading program code by the mcu i tself. this feature allows flexible applica- tion software updates controlled by the mcu using a flash-resident boot loader program. the boot loader program can use any available data inte rface and associated protocol to read code and write (program) that code into the flash memory , or read the code from the program mem- ory. the program code within the boot loader sectio n has the capability to write into the entire flash, including the boot loader memory. the boot l oader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and the bo ot loader has two separate sets of boot lock bits which can be set independently. this give s the user a unique flexibility to select differ- ent levels of protection. 24.1 features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexib le protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 25-11 on page 340 ) used during programming. the page organization does not affect normal operation. 24.2 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 24-2 ). the size of the different sections is configured by the bootsz fuses as shown in table 24-6 on page 333 and figure 24-2 . these two sections can have different level of protection since they have different sets of lock bits. 24.2.1 as - application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section ca n be selected by the application boot lock bits (blb02 and blb01 bits), see table 24-2 on page 324 . the application section can never store any boot loader code since the spm instruction is d isabled when executed from the application section. 24.2.2 bls ? boot loader section while the application section is used for storing t he application code, the the boot loader soft- ware must be located in the bls since the spm instr uction can initiate a programming when executing from the bls only. the spm instruction ca n access the entire flash, including the bls itself. the protection level for the boot loade r section can be selected by the boot loader lock bits (blb12 and blb11 bits), see table 24-3 on page 324 . 24.3 read-while-write and no read-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft- ware update is dependent on which address that is b eing programmed. in addition to the two
321 7682c?auto?04/08 at90can32/64/128 sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-while-wri te (rww) section and the no read-while- write (nrww) section. the limit between the rww- an d nrww sections is given in table 24- 7 on page 333 and figure 24-2 on page 323 . the main difference between the two sections is: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section dur- ing a boot loader software operation. the syntax ?r ead-while-write section? refers to which section that is being programmed (erased or written ), not which section that actually is being read during a boot loader software update. 24.3.1 rww ? read-while-write section if a boot loader software update is programming a p age inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on- going programming, the software must ensure that th e rww section never is being read. if the user software is trying to read code that is locate d inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programming, t he software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sec- tion. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store program memory control and status register (spmcsr) will be read as logical one as long as the rww section is blocke d for reading. after a programming is com- pleted, the rwwsb must be cleared by software befor e reading code located in the rww section. see ?store program memory control and status regist er ? spmcsr? on page 325. for details on how to clear rwwsb. 24.3.2 nrww ? no read-while-write section the code located in the nrww section can be read wh en the boot loader software is updating a page in the rww section. when the boot loader cod e updates the nrww section, the cpu is halted during the entire page erase or page writ e operation. table 24-1. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no
322 7682c?auto?04/08 at90can32/64/128 figure 24-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation
323 7682c?auto?04/08 at90can32/64/128 figure 24-2. memory sections note: the parameters in the figure above are given i n table 24-6 on page 333 . 24.4 boot loader lock bits if no boot loader capability is needed, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to select different l evels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flash end application flash section flash end end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader
324 7682c?auto?04/08 at90can32/64/128 ? allow software update in the entire flash. see table 24-2 and table 24-3 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they ca n be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. similarly, the general r ead/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm (load progra m memory / store program memory) instructions, if it is attempted. note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed 24.5 entering the boot loader program entering the boot loader takes place by a jump or c all from the application program. this may be initiated by a trigger such as a command receive d via usart, or spi interface. alternatively, the boot reset fuse can be programmed so that the r eset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the applica - tion code is loaded, the program can start executin g the application code. note that the fuses cannot be changed by the mcu itself. this means tha t once the boot reset fuse is pro- table 24-2. boot lock bit0 protection modes (application sectio n) (1) lock bit mode blb02 blb01 protection 1 1 1 no restrictions for spm or lpm accessing the app lication section. 2 1 0 spm is not allowed to write to the application s ection. 3 0 0 spm is not allowed to write to the application sect ion, and lpm executing from the boot loader section is not allow ed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 4 0 1 lpm executing from the boot loader section is not a llowed to read from the application section. if interrupt vec tors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 24-3. boot lock bit1 protection modes (boot loader sectio n) (1) lock bit mode blb12 blb11 protection 1 1 1 no restrictions for spm or lpm accessing the boot l oader section. 2 1 0 spm is not allowed to write to the boot loader s ection. 3 0 0 spm is not allowed to write to the boot loader sect ion, and lpm executing from the application section is not allow ed to read from the boot loader section. if interrupt vectors are p laced in the application section, interrupts are disabled while executing from the boot loader section. 4 0 1 lpm executing from the application section is not a llowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section.
325 7682c?auto?04/08 at90can32/64/128 grammed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed 24.5.1 store program memory control and status regis ter ? spmcsr the store program memory control and status registe r contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready inte rrupt will be executed as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi- ated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared i f the rwwsre bit is written to one after a self-programming operation is completed. alternativ ely the rwwsb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? res: reserved bit this bit is a reserved bit in the at90can32/64/128 and always read as zero. ? bit 4 ? rwwsre: read-while-write section read enab le when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardw are). to re-enable the rww section, the user software must wait until the programming is co mpleted (spmen will be cleared). then, if the rwwsre bit is written to one at the same time a s spmen, the next spm instruction within four clock cycles re-enables the rww section. the r ww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is set). if the rwwsre bit is writ- ten while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as s pmen, the next spm instruction within four clock cycles sets boot lock bits, according to the data i n r0. the data in r1 and the address in the z- pointer are ignored. the blbset bit will automatica lly be cleared upon completion of the lock bit set, or if no spm instruction is executed withi n four clock cycles. table 24-4. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 24-6 on page 333 ) bit 7 6 5 4 3 2 1 0 spmie rwwsb ? rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0
326 7682c?auto?04/08 at90can32/64/128 an lpm instruction within three cycles after blbset and spmen are set in the spmcsr reg- ister, will read either the lock bits or the fuse b its (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on p age 329 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as s pmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completion of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire p age write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as s pmen, the next spm instruction within four clock cycles executes page erase. the page address is tak en from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bit will a uto-clear upon completion of a page erase, or if no spm instruction is executed within four cl ock cycles. the cpu is halted during the entire page write operation if the nrww section is address ed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next f our clock cycles. if written to one together with either rwwsre, blbset, pgwrt? or pgers, the followi ng spm instruction will have a spe- cial meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buff er addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will auto-c lear upon completion of an spm instruction, or if no spm instruction is executed within four cl ock cycles. during page erase and page write, the spmen bit remains high until the operation is c ompleted. writing any other combination than ?10001?, ?01001? , ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 24.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. the z pointer consists of the z-registers zl and zh in the register file, and rampz in the i/ o space. the number of bits actually used is implementation dependent. note that the rampz regis ter is only implemented when the pro- gram space is larger than 64k bytes. since the flash is organized in pages (see table 25-11 on page 340 ), the program counter can be treated as having two different sections. one se ction, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 24-3 . note that the page erase and page write operation s are addressed independently. therefore it is of major importance that the boot loader software addresses the bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 rampz ? ? ? ? ? ? ? rampz0 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7 z6 z5 z4 z3 z2 z1 z0 7 6 5 4 3 2 1 0
327 7682c?auto?04/08 at90can32/64/128 same page in both the page erase and page write ope ration. once a programming operation is initiated, the address is latched and the z-pointer can be used for other operations. the (e)lpm instruction use the z-pointer to store t he address. since this instruction addresses the flash byte-by-byte, also bit z0 of the z-pointe r is used. figure 24-3. addressing the flash during spm (1) note: 1. the different variables used in figure 24-3 are listed in table 24-8 on page 334 . 24.7 self-programming the flash the program memory is updated in a page by page fas hion. before programming a page with the data stored in the temporary page buffer, the p age must be erased. the temporary page buffer is filled one word at a time using spm and t he buffer can be filled either before the page erase command or between a page erase and a page wr ite operation: alternative 1 : fill the buffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2 : fill the buffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write program memory 0 1 23 z - pointer bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word page pcword[pagemsb:0]: 00 01 02 pageend page pcword pcpage pcmsb pagemsb program counter
328 7682c?auto?04/08 at90can32/64/128 if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. when using alternative 1, the boot loader provides an effective read-modify-w rite feature which allows the user software to first read the page, do the necessary changes, a nd then write back the modified data. if alter- native 2 is used, it is not possible to read the ol d data while loading since the page is already erased. the temporary page buffer can be accessed i n a random sequence. it is essential that the page address used in both the page erase and pa ge write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 331 for an assembly code example. 24.7.1 performing page erase by spm to execute page erase, set up the address in the z- pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z -register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section ca n be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 24.7.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four cl ock cycles after writing spmcsr. the content of pcword in the z-register is used to addr ess the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. not e that it is not possible to write more than one time to each address without erasing the tempor ary buffer. if the eeprom is written in the middle of an spm pa ge load operation, all data loaded will be lost. 24.7.3 performing a page write to execute page write, set up the address in the z- pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other b its in the z-pointer will be ignored during this operation. ? page write to the rww section: the nrww section ca n be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 24.7.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt will generate a constant interrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interr upt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 60 . 24.7.5 consideration while updating bls special care must be taken if the user allows the b oot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write t o the boot loader itself can corrupt the entire boot loader, and further software updates mi ght be impossible. if it is not necessary to
329 7682c?auto?04/08 at90can32/64/128 change the boot loader software itself, it is recom mended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 24.7.6 prevent reading the rww section during self-p rogramming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the sp mcsr will be set as long as the rww section is busy. during self-programming the interr upt vector table should be moved to the bls as described in ?interrupts? on page 60 , or the interrupts must be disabled. before addres sing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 331 for an example. 24.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writ ing spmcsr. the only accessible lock bits are the boot lock bits that may prevent the applica tion and boot loader section from any soft- ware update by the mcu. see table 24-2 and table 24-3 for how the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the correspo nding boot lock bit will be programmed if an spm instruction is executed within four cycles afte r blbset and spmen are set in spmcsr. the z-pointer is don?t care during this operation, but for future compatibility it is recommended to load the z-pointer with 0x0001 (same as used for re ading the lock bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 i n r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be r ead during the operation. 24.7.8 eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prev ented during the eeprom write operation. it is recommended that the user checks the status bit (eewe) in the eecr register and verifies that the bit is cleared before writing to the spmcs r register. 24.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an lpm instruc- tion is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the de stination register. the blbset and spmen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycles or no spm instruction is ex ecuted within four cpu cycles. when blb- set and spmen are cleared, lpm will work as describ ed in the instruction set manual. bit 7 6 5 4 3 2 1 0 r0 1 1 blb12 blb11 blb02 blb01 1 1 bit 7 6 5 4 3 2 1 0 rd (z=0x0001) ? ? blb12 blb11 blb02 blb01 lb2 lb1
330 7682c?auto?04/08 at90can32/64/128 the algorithm for reading the fuse low byte is simi lar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an lpm instruction i s executed within three cycles after the blbset and spmen bits are set in the spmcsr, the va lue of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 25-5 on page 337 for a detailed description and mapping of the fuse low by te. similarly, when reading the fuse high byte, load 0x 0003 in the z-pointer. when an lpm instruc- tion is executed within three cycles after the blbs et and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be loade d in the destination register as shown below. refer to table 25-4 on page 336 for detailed description and mapping of the fuse h igh byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within three cycles after the blbset an d spmen bits are set in the spmcsr, the value of the extended fuse byte (efb) will be loade d in the destination register as shown below. refer to table 25-3 on page 336 for detailed description and mapping of the extend ed fuse byte. fuse and lock bits that are programmed, will be rea d as zero. fuse and lock bits that are unprogrammed, will be read as one. 24.7.10 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the su pply voltage is too low for the cpu and the flash to operate proper ly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two sit uations when the voltage is too low. ? first, a regular write sequence to the flash requi res a minimum voltage to operate correctly. ? secondly, the cpu itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in t he system, program the boot loader lock bits to prevent any boot loader software updat es. 2. keep the avr reset active (low) during periods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an ext ernal low v cc reset protection circuit can be used. if a reset occurs while a write operat ion is in progress, the write operation will be completed provided that the power supply vo ltage is sufficient. bit 7 6 5 4 3 2 1 0 rd (z=0x0000) flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 7 6 5 4 3 2 1 0 rd (z=0x0003) fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 7 6 5 4 3 2 1 0 rd (z=0x0002) ? ? ? ? efb3 efb2 efb1 efb0
331 7682c?auto?04/08 at90can32/64/128 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from uninten tional writes. 24.7.11 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 24-5 shows the typical pro- gramming time for flash accesses from the cpu. 24.7.12 simple assembly code example for a boot load er ;- the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by t he y-pointer ; the first data location in flash is pointed to by the z-pointer ;- error handling is not included ;- the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code insi de nrww section can ; be read during self-programming (page erase and p age write). ;- registers used: r0, r1, temp1 (r16), temp2 (r17) , looplo (r24), ; loophi (r25), spmcsrval (r20) ; storing and restoring of registers is not include d in the routine ; register usage can be optimized at the expense of code size ;- it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disable d. .equ pagesizeb = pagesize*2 ;pagesizeb is page size i n bytes, not words .org smallbootstart write_page: ; page erase ldi spmcsrval, (1< 332 7682c?auto?04/08 at90can32/64/128 sbci zh, high(pagesizeb) ;not required for pagesizeb< =256 ldi spmcsrval, (1< 333 7682c?auto?04/08 at90can32/64/128 24.7.13 boot loader parameters in table 24-6 through table 24-8 , the parameters used in the description of the sel f-program- ming are given. notes: 1. the different bootsz fuse configurations ar e shown in figure 24-2 notes: 1. for details about these two section, see ?nrww ? no read-while-write section? on page 321 and ?rww ? read-while-write section? on page 321 . table 24-6. boot size configuration (word addresses) (1) device bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) at90can32 1 1 512 words 4 0x0000 - 0x3dff 0x3e00 - 0x3fff 0x3dff 0x3 e00 1 0 1024 words 8 0x0000 - 0x3bff 0x3c00 - 0x3fff 0x3bff 0x 3c00 0 1 2048 words 16 0x0000 - 0x37ff 0x3800 - 0x3fff 0x37ff 0 x3800 0 0 4096 words 32 0x0000 - 0x2fff 0x3000 - 0x3fff 0x2fff 0 x3000 at90can64 1 1 512 words 4 0x0000 - 0x7dff 0x7e00 - 0x7fff 0x7dff 0x7 e00 1 0 1024 words 8 0x0000 - 0x7bff 0x7c00 - 0x7fff 0x7bff 0x 7c00 0 1 2048 words 16 0x0000 - 0x77ff 0x7800 - 0x7fff 0x77ff 0 x7800 0 0 4096 words 32 0x0000 - 0x6fff 0x7000 - 0x7fff 0x6fff 0 x7000 at90can128 1 1 512 words 4 0x0000 - 0xfdff 0xfe00 - 0xffff 0xfdff 0xf e00 1 0 1024 words 8 0x0000 - 0xfbff 0xfc00 - 0xffff 0xfbff 0x fc00 0 1 2048 words 16 0x0000 - 0xf7ff 0xf800 - 0xffff 0xf7ff 0 xf800 0 0 4096 words 32 0x0000 - 0xefff 0xf000 - 0xffff 0xefff 0 xf000 table 24-7. read-while-write limit (word addresses) (1) device section pages address at90can32 read-while-write section (rww) 96 0x0000 - 0x2fff no read-while-write section (nrww) 32 0x3000 - 0x3fff at90can64 read-while-write section (rww) 224 0x0000 - 0x6fff no read-while-write section (nrww) 32 0x7000 - 0x7fff at90can128 read-while-write section (rww) 480 0x0000 - 0xefff no read-while-write section (nrww) 32 0xf000 - 0xffff
334 7682c?auto?04/08 at90can32/64/128 notes: 1. see ?addressing the flash during self-programming? on p age 326 for details about the use of z-pointer during self-programming. 2. z0: should be zero for all spm commands, byte sel ect for the (e)lpm instruction. 3. the z-register is only 16 bits wide. bit 16 is lo cated in rampz register in i/o map. table 24-8. explanation of different variables used in figure 24-3 on page 327 and the mapping to the z-pointer (1) device variable name variable value corresponding z-value description (2) at90can32 pcmsb 13 most significant bit in the program counter. (the program counter is 14 bits pc[13:0]) pagemsb 6 most significant bit which is used to address the w ords within one page (128 words in a page requires 7 bits pc [6:0]). zpcmsb z14 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-register that is mapped to pagemsb. becaus e z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[13:7] z14:z7 program counter page address: p age select, for page erase and page write. pcword pc[6:0] z7:z1 program counter word address: word select, for fill ing temporary buffer (must be zero during page write operation). at90can64 pcmsb 14 most significant bit in the program counter. (the program counter is 15 bits pc[14:0]) pagemsb 6 most significant bit which is used to address the w ords within one page (128 words in a page requires 7 bits pc [6:0]). zpcmsb z15 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-register that is mapped to pagemsb. becaus e z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[14:7] z15:z7 program counter page address: p age select, for page erase and page write. pcword pc[6:0] z7:z1 program counter word address: word select, for fill ing temporary buffer (must be zero during page write operation). at90can128 pcmsb 15 most significant bit in the program counter. (the program counter is 16 bits pc[15:0]) pagemsb 6 most significant bit which is used to address the w ords within one page (128 words in a page requires 7 bits pc [6:0]). zpcmsb z16 (3) bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-register that is mapped to pagemsb. becaus e z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[15:7] z16 (3) :z7 program counter page address: page select, for p age erase and page write. pcword pc[6:0] z7:z1 program counter word address: word select, for fill ing temporary buffer (must be zero during page write operation).
335 7682c?auto?04/08 at90can32/64/128 25. memory programming 25.1 program and data memory lock bits the at90can32/64/128 provides six lock bits which c an be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 25-2 . the lock bits can only be erased to ?1? with the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed . table 25-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 25-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 2 1 0 further programming of the flash and eeprom is disa bled in parallel and serial programming mode. the fuse bits are locked i n both serial and parallel programming mode. (1) 3 0 0 further programming and verification of the flash a nd eeprom is disabled in parallel and serial programming mode. the boot l ock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 1 1 1 no restrictions for spm (store program memory) or l pm (load program memory) accessing the application section. 2 1 0 spm is not allowed to write to the application s ection. 3 0 0 spm is not allowed to write to the application sect ion, and lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boo t loader section, interrupts are disabled while executing from the application s ection. 4 0 1 lpm executing from the boot loader section is not a llowed to read from the application section. if interrupt vectors are place d in the boot loader section, interrupts are disabled while executing fr om the application section. blb1 mode blb12 blb11 1 1 1 no restrictions for spm or lpm accessing the boo t loader section.
336 7682c?auto?04/08 at90can32/64/128 notes: 1. program the fuse bits and boot lock bits be fore programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 25.2 fuse bits the at90can32/64/128 has three fuse bytes. table 25-3 , table 25-4 and table 25-5 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they ar e programmed. note: 1. see table 7-2 on page 54 for bodlevel fuse decoding. 2 1 0 spm is not allowed to write to the boot loader s ection. 3 0 0 spm is not allowed to write to the boot loader sect ion, and lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the app lication section, interrupts are disabled while executing from the boot loader s ection. 4 0 1 lpm executing from the application section is not a llowed to read from the boot loader section. if interrupt vectors are place d in the application section, interrupts are disabled while executing fr om the boot loader section. table 25-2. lock bit protection modes (1)(2) (continued) memory lock bits protection type table 25-3. extended fuse byte fuse extended byte bit no description default value ? 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 bodlevel2 (1) 3 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (1) 1 brown-out detector trigger level 1 (unprogrammed) ta0sel 0 (reserved for factory tests) 1 (unprogrammed) table 25-4. fuse high byte fuse high byte bit no description default value ocden (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtagen (5) 6 enable jtag 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data downloading 0 (programmed, spi prog. enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved)
337 7682c?auto?04/08 at90can32/64/128 notes: 1. the spien fuse is not accessible in serial programming mode. 2. the default value of bootsz1..0 results in maximu m boot size. see table 24-6 on page 333 for details. 3. see ?watchdog timer control register ? wdtcr? on page 5 7 for details. 4. never ship a product with the ocden fuse programm ed regardless of the setting of lock bits and jtagen fuse. a programmed ocden fuse enables so me parts of the clock system to be running in all sleep modes. this may increase th e power consumption. 5. if the jtag interface is left unconnected, the jt agen fuse should if possible be disabled. this to avoid static current at the tdo pin in the jtag interface. 6. the boot sizes of all the avr can microcontroller s are identical. 7. due to the flash size, the boot reset address dif fers from one avr can microcontroller to another. notes: 1. the default value of sut1..0 results in max imum start-up time for the default clock source. see table 5-8 on page 42 for details. 2. the default setting of cksel3..0 results in inter nal rc oscillator @ 8 mhz. see table 5-1 on page 38 for details. 3. the ckout fuse allow the system clock to be outpu t on port pc7. see ?clock output buffer? on page 43 for details. 4. see ?system clock prescaler? on page 44 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bit s before programming the lock bits. 25.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leav es programming mode. this does not apply to the eesave fuse which will take effect once it is p rogrammed. the fuses are also latched on power-up in normal mode. bootsz1 2 select boot size (6) (see table 24-6 for details) 0 (programmed) (2) bootsz0 1 select boot size (6) (see table 24-6 for details) 0 (programmed) (2) bootrst 0 select reset vector (7) (see table 24-6 for details) 1 (unprogrammed) table 25-5. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) table 25-4. fuse high byte (continued) fuse high byte bit no description default value
338 7682c?auto?04/08 at90can32/64/128 25.3 signature bytes all atmel microcontrollers have a three-byte signat ure code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. 25.4 calibration byte the at90can32/64/128 has a byte calibration value f or the internal rc oscillator. this byte resides in the high byte of address 0x000 in the si gnature address space. during reset, this byte is automatically written into the osccal register t o ensure correct frequency of the calibrated rc oscillator. 25.5 parallel programming overview this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90can32/64/128. pulses are assumed to be at least 250 ns unless otherwise noted. 25.5.1 signal names in this section, some pins of the at90can32/64/128 are referenced by signal names describing their functionality during parallel programming, se e figure 25-1 and table 25-7 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 25-9 . when pulsing wr or oe , the command loaded determines the action executed . the different commands are shown in table 25-10 . table 25-6. signature bytes device address value signature byte description at90can32 0 0x1e indicates manufactured by atmel 1 0x95 indicates 32 kb flash memory 2 0x81 indicates at90can32 device when address 1 cont ains 0x95 at90can64 0 0x1e indicates manufactured by atmel 1 0x96 indicates 64 kb flash memory 2 0x81 indicates at90can64 device when address 1 cont ains 0x96 at90can128 0 0x1e indicates manufactured by atmel 1 0x97 indicates 128 kb flash memory 2 0x81 indicates at90can128 device when address 1 con tains 0x97
339 7682c?auto?04/08 at90can32/64/128 figure 25-1. parallel programming 25.5.2 pin mapping 25.5.3 commands vcc +2.7 - +5.5v gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pb7 - pb0 da ta reset pd7 +12 v bs1 xa0 xa1 oe rdy/bsy pagel pa0 wr bs2 avcc +2.7 - +5.5v table 25-7. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command. oe pd2 i output enable (active low). wr pd3 i write pulse (active low). bs1 pd4 i byte select 1 (?0? selects low byte, ?1? sel ects high byte). xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load. bs2 pa0 i byte select 2 (?0? selects low byte, ?1? sel ects 2?nd high byte). data pb7-0 i/o bi-directional data bus (output when oe is low). table 25-8. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0
340 7682c?auto?04/08 at90can32/64/128 25.5.4 parameters table 25-9. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determ ined by bs1). 1 0 load command 1 1 no action, idle table 25-10. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 25-11. no. of words in a page and no. of pages in the flas h device flash size page size pcword no. of pages pcpage pc msb at90can32 16k words 128 words pc[6:0] 128 pc[13:7] 13 at90can64 32k words 128 words pc[6:0] 256 pc[14:7] 14 at90can128 64k words 128 words pc[6:0] 512 pc[15:7] 15 table 25-12. no. of words in a page and no. of pages in the eepr om device eeprom size page size pcword no. of pages pcpage e eamsb at90can32 1k bytes 8 bytes eea[2:0] 128 eea[9:3] 9 at90can64 2k bytes 8 bytes eea[2:0] 256 eea[10:3] 10 at90can128 4k bytes 8 bytes eea[2:0] 512 eea[11:3] 11
341 7682c?auto?04/08 at90can32/64/128 25.6 parallel programming 25.6.1 enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply power between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 25-8 on page 339 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns af ter +12v has been applied to reset , will cause the device to fail entering programmin g mode. 5. wait at least 50 s before sending a new command. 25.6.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the cont ents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip e rase. ? address high byte needs only be loaded before prog ramming or reading a new 256 word window in flash or 256 byte eeprom. this considerat ion also applies to signature bytes reading. 25.6.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been complet ely erased. the fuse bits are not changed. a chip erase must be performed before the flash and/or eeprom are reprogrammed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loadin g. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the comma nd. 5. give wr a negative pulse. this starts the chip erase. rdy/ bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. note: 1. the eeprom memory is preserved during chip e rase if the eesave fuse is programmed. 25.6.4 programming the flash the flash is organized in pages, see table 25-11 on page 340 . when programming the flash, the program data is latched into a page buffer. thi s allows one page of program data to be pro- grammed simultaneously. the following procedure des cribes how to program the entire flash memory: a : load command ?write flash?
342 7682c?auto?04/08 at90can32/64/128 1. set xa1, xa0 to ?10?. this enables command loadin g. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the comma nd. b : load address low byte 1. set xa1, xa0 to ?00?. this enables address loadin g. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the addre ss low byte. c : load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d : load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e : latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the dat a bytes. (see figure 25-3 for signal waveforms) f : repeat b through e until the entire buffer is fil led or until all data within the page is loaded. while the lower bits in the address are mapped to w ords within the page, the higher bits address the pages within the flash. this is illustr ated in figure 25-2 on page 343 . note that if less than eight bits are required to address wor ds in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g : load address high byte 1. set xa1, xa0 to ?00?. this enables address loadin g. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the addre ss high byte. h : program page 1. give wr a negative pulse. this starts programming of the e ntire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 25-3 for signal waveforms). i : repeat b through h until the entire flash is prog rammed or until all data has been programmed. j : end page programming
343 7682c?auto?04/08 at90can32/64/128 1. 1. set xa1, xa0 to ?10?. this enables command loa ding. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the comma nd, and the internal write signals are reset. figure 25-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 25-11 on page 340 . figure 25-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters refer to the programming description above. program memory word address within a page page address within the flash instruction word page pcword[pagemsb:0]: 00 01 02 pageend page pcword pcpage pcmsb pagemsb program counter 0x10 addr. low addr. high data low data high addr. low data low data high rdy/bsy wr oe reset +12v pagel bs2 data xa1 xa0 bs1 xtal1 xx xx xx a b c d e b c d e g h f
344 7682c?auto?04/08 at90can32/64/128 25.6.5 programming the eeprom the eeprom is organized in pages, see table 25-12 on page 340 . when programming the eeprom, the program data is latched into a page buf fer. this allows one page of data to be programmed simultaneously. the programming algorith m for the eeprom data memory is as follows (refer to ?programming the flash? on page 341 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k : repeat 3 through 5 until the entire buffer is fil led. l : program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts programming of the e eprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 25-4 for signal waveforms). figure 25-4. programming the eeprom waveforms 25.6.6 reading the flash the algorithm for reading the flash memory is as fo llows (refer to ?programming the flash? on page 341 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte ca n now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 0x11 addr. high addr. low data addr. low data xx xx a g b c e b c e l k rdy/bsy wr oe reset +12v pagel bs2 data xa1 xa0 bs1 xtal1
345 7682c?auto?04/08 at90can32/64/128 25.6.7 reading the eeprom the algorithm for reading the eeprom memory is as f ollows (refer to ?programming the flash? on page 341 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can n ow be read at data. 5. set oe to ?1?. 25.6.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 341 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and b it n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 25.6.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 341 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and b it n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 25.6.10 programming the extended fuse bits the algorithm for programming the extended fuse bit s is as follows (refer to ?programming the flash? on page 341 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and b it n = ?1? erases the fuse bit. 3. set bs1 to ?0? and bs2 to ?1?. this selects exten ded data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs2 to ?0?. this selects low data byte.
346 7682c?auto?04/08 at90can32/64/128 figure 25-5. programming the fuses waveforms 25.6.11 programming the lock bits the algorithm for programming the lock bits is as f ollows (refer to ?programming the flash? on page 341 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the l ock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 25.6.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 341 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of t he fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of t he fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the st atus of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of t he lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. 0x40 data xx a c 0x40 data xx a c write fuse low byte write fuse high byte 0x40 data xx a c write extended fuse byte xtal1 bs2 reset +12v rdy/bsy wr oe pagel data xa1 xa0 bs1
347 7682c?auto?04/08 at90can32/64/128 figure 25-6. mapping between bs1, bs2 and the fuse and lock bits during read 25.6.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to ?programming the flash? on page 341 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data . 4. set oe to ?1?. 25.6.14 reading the calibration byte the algorithm for reading the calibration byte is a s follows (refer to ?programming the flash? on page 341 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can n ow be read at data. 4. set oe to ?1?. 25.7 spi serial programming overview this section describes how to serial program and ve rify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90 can32/64/128. 25.7.1 signal names both the flash and eeprom memory arrays can be prog rammed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). after reset is set low, the programming enable instruction nee ds to be executed first before program/erase operations can be executed. no te, in table 25-13 on page 348 , the pin mapping for spi programming is listed. not all part s use the spi pins dedicated for the internal spi interface. note that throughout the description about serial downloading, mosi and miso are used to describe the serial data in and serial data out respectively. for at90can32/64/128 these pins are mapped to pdi (pe0) and pdo (pe1). bs2 data 0 1 bs2 extended fuse byte fuse low byte 0 1 fuse high byte lock bits bs1 0 1
348 7682c?auto?04/08 at90can32/64/128 figure 25-7. serial programming and verify (1) notes: 1. if the device is clocked by the internal os cillator, it is no need to connect a clock source t o the xtal1 pin. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the con tent of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be pre sent. the minimum low and high periods for the serial clock (sck) input are defined as fol lows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck 12 mhz 25.7.2 pin mapping 25.7.3 parameters the flash parameters are given in table 25-11 on page 340 and the eeprom parameters in table 25-12 on page 340 . 25.8 spi serial programming when writing serial data to the at90can32/64/128, d ata is clocked on the rising edge of sck. when reading data from the at90can32/64/128, data i s clocked on the falling edge of sck. to program and verify the at90can32/64/128 in the s erial programming mode, the following sequence is recommended (see four byte instruction formats in table 25-15 ): vcc +2.7 - +5. gnd xtal1 pb1 reset pdo pe1 pe0 pdi sck avcc +2.7 - +5. table 25-13. pin mapping serial programming symbol pins i/o description mosi (pdi) pe0 i serial data in miso (pdo) pe1 o serial data out sck pb1 i serial clock
349 7682c?auto?04/08 at90can32/64/128 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial program ming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will not work if the communication is out of syn- chronization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. w hether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enabl e command. 4. the flash is programmed one page at a time. the m emory page is loaded one byte at a time by supplying the 7 lsb of the address and da ta together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a gi ven address. the program memory page is stored by loading the write program memory page instruction with the 9 msb of the address. if polling is not used, the user mu st wait at least t wd_flash before issuing the next page. (see table 25-14 .) accessing the serial programming interface befor e the flash write operation completes can result in i ncorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instructio n. an eeprom memory location is first automatically erased before new data is writt en. if polling is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 25-14 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output mi so. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn v cc power off. 25.8.1 data polling flash when a page is being programmed into the flash, rea ding an address location within the page being programmed will give the value 0xff. at the t ime the device is ready for a new page, the programmed value will read correctly. this is used to determine when the next page can be writ- ten. note that the entire page is written simultane ously and any address within the page can be used for polling. data polling of the flash will no t work for the value 0xff, so when programming this value, the user will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains 0xff in all locations , programming of addresses that are meant to contain 0xff, can be skipped. see table 25-14 for t wd_flash value. 25.8.2 data polling eeprom when a new byte has been written and is being progr ammed into eeprom, reading the address location being programmed will give the val ue 0xff. at the time the device is ready for a new byte, the programmed value will read correctl y. this is used to determine when the next byte can be written. this will not work for the val ue 0xff, but the user should have the following in mind: as a chip-erased device contains 0xff in a ll locations, programming of addresses that are meant to contain 0xff, can be skipped. this doe s not apply if the eeprom is re-pro-
350 7682c?auto?04/08 at90can32/64/128 grammed without chip erasing the device. in this ca se, data polling cannot be used for the value 0xff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 25-14 for t wd_eeprom value. figure 25-8. serial programming waveforms table 25-14. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_fuse 4.5 ms t wd_flash 4.5 ms t wd_eeprom 9.0 ms t wd_erase 9.0 ms msb lsb lsb serial clock input (sck) serial data input (mosi-pdi) (miso-pdo) sample serial data output msb table 25-15. serial programming instruction set set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction instruction format (1) operation (1) byte 1 byte 2 (2) byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. read program memory 0010 h 000 aaaa aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . load program memory page 0100 h 000 000x xxxx x bbb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 aaaa aaaa b xxx xxxx xxxx xxxx write program memory page at address a : b . read eeprom memory 1010 0000 000x aaaa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 000x aaaa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b .
351 7682c?auto?04/08 at90can32/64/128 notes: 1. all bytes are represented by binary digits (0b...). 2. address bits exceeding pcmsb and eeamsb (see table 25-11 on page 340 and table 25-12 on page 340 ) are don?t care. 25.9 jtag programming overview programming through the jtag interface requires con trol of the four jtag specific pins: tck, tms, tdi, and tdo. control of the reset and clock p ins is not required. to be able to use the jtag interface, the jtagen fu se must be programmed. the device is default shipped with the fuse programmed. in additi on, the jtd bit in mcucr must be cleared. alternatively, if the jtd bit is set, the external reset can be forced low. then, the jtd bit will be cleared after two chip clocks, and the jtag pins ar e available for programming. this provides a means of using the jtag pins as normal port pins in running mode while still allowing in-sys- tem programming via the jtag interface. note that t his technique can not be used when using load eeprom memory page (page access) 1100 0001 0000 0000 0000 0 bbb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 000x aaaa bbbb b000 xxxx xxxx write eeprom page at address a : b . read lockbits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0?= programmed , ?1?= unprogrammed . see table 25-1 on page 335 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bit s. see table 25-1 on page 335 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse low bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 25-5 on page 337 for details. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 25-4 on page 336 for details. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx xxxx iiii set bits = ?0? to program, ?1? to unprogram. see table 25-3 on page 336 for details. read fuse low bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0?= programmed , ?1?= unprogrammed . see table 25-5 on page 337 for details. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0?=programmed, ?1?=unprogrammed. see table 25-4 on page 336 for details. read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0?=programmed, ?1?=unprogrammed. see table 25-3 on page 336 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying anoth er command. table 25-15. serial programming instruction set (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction instruction format (1) operation (1) byte 1 byte 2 (2) byte 3 byte4
352 7682c?auto?04/08 at90can32/64/128 the jtag pins for boundary-scan or on-chip debug. i n these cases the jtag pins must be ded- icated for this purpose. during programming the clock frequency of the tck i nput must be less than the maximum fre- quency of the chip. the system clock prescaler can not be used to divide the tck clock input into a sufficiently low frequency. as a definition in this datasheet, the lsb is shift ed in and out first of all shift registers. 25.9.1 programming specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 instructions. the jtag instructions useful for programming are listed below. the opcode for each instruction is shown behind the instruction name in hex format. the text describes which data register is selected as path b etween tdi and tdo for each instruction. the run-test/idle state of the tap controller is us ed to generate internal clocks. it can also be used as an idle state between jtag sequences. the s tate machine sequence for changing the instruction word is shown in figure 25-9 . figure 25-9. state machine sequence for changing the instruction word t est-logic-reset run-t est/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1
353 7682c?auto?04/08 at90can32/64/128 25.9.1.1 avr_reset (0xc) the avr specific public jtag instruction for settin g the avr device in the reset mode or taking the device out from the reset mode. the tap control ler is not reset by this instruction. the one bit reset register is selected as data register. no te that the reset will be active as long as there is a logic ?one? in the reset chain. the output fro m this chain is not latched. the active states are: ? shift-dr: the reset register is shifted by the tck input. 25.9.1.2 prog_enable (0x4) the avr specific public jtag instruction for enabli ng programming via the jtag port. the 16- bit programming enable register is selected as data register. the active states are the following: ? shift-dr: the programming enable signature is shif ted into the data register. ? update-dr: the programming enable signature is com pared to the correct value, and programming mode is entered if the signature is val id. 25.9.1.3 prog_commands (0x5) the avr specific public jtag instruction for enteri ng programming commands via the jtag port. the 15-bit programming command register is se lected as data register. the active states are the following: ? capture-dr: the result of the previous command is loaded into the data register. ? shift-dr: the data register is shifted by the tck input, shifting out the result of the previous command and shifting in the new command. ? update-dr: the programming command is applied to t he flash inputs ? run-test/idle: one clock cycle is generated, execu ting the applied command (not always required, see table 25-16 below). 25.9.1.4 prog_pageload (0x6) the avr specific public jtag instruction to directl y load the flash data page via the jtag port. an 8-bit flash data byte register is selected as th e data register. this is physically the 8 lsbs of the programming command register. the active sta tes are the following: ? shift-dr: the flash data byte register is shifted by the tck input. ? update-dr: the content of the flash data byte regi ster is copied into a temporary register. a write sequence is initiated that within 11 tck cy cles loads the content of the temporary register into the flash page buffer. the avr automa tically alternates between writing the low and the high byte for each new update-dr state, sta rting with the low byte for the first update-dr encountered after entering the prog_pagel oad command. the program counter is pre-incremented before writing the low b yte, except for the first written byte. this ensures that the first data is written to the addre ss set up by prog_commands, and loading the last location in the page buffer does n ot make the program counter increment into the next page. 25.9.1.5 prog_pageread (0x7) the avr specific public jtag instruction to directl y capture the flash content via the jtag port. an 8-bit flash data byte register is selected as th e data register. this is physically the 8 lsbs of the programming command register. the active sta tes are the following:
354 7682c?auto?04/08 at90can32/64/128 ? capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates between reading the low and the high byte for each new capture-dr state, starting with the low by te for the first capture-dr encountered after entering the prog_pageread command. the progr am counter is post-incremented after reading each high byte, including the first r ead byte. this ensures that the first data is captured from the first address set up by prog_comm ands, and reading the last location in the page makes the program counter increment int o the next page. ? shift-dr: the flash data byte register is shifted by the tck input. 25.9.2 data registers the data registers are selected by the jtag instruc tion registers described in section ?program- ming specific jtag instructions? on page 352 . the data registers relevant for programming operations are: ? reset register ? programming enable register ? programming command register ? flash data byte register 25.9.2.1 reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering programm ing mode. a high value in the reset register corresponds to p ulling the external reset low. the part is reset as long as there is a high value present in the res et register. depending on the fuse settings for the clock options, the part will remain reset f or a reset time-out period (refer to ?clock sources? on page 38 ) after releasing the reset register. the output fr om this data register is not latched, so the reset will take place immediately, as shown in figure 23-2 on page 301 . 25.9.2.2 programming enable register the programming enable register is a 16-bit registe r. the contents of this register is compared to the programming enable signature, binary code 0b 1010_0011_0111_0000. when the con- tents of the register is equal to the programming e nable signature, programming via the jtag port is enabled. the register is reset to 0 on powe r-on reset, and should always be reset when leaving programming mode. figure 25-10. programming enable register tdi tdo d a t a = d q clockdr & prog_enable programming enable 0xa370
355 7682c?auto?04/08 at90can32/64/128 25.9.2.3 programming command register the programming command register is a 15-bit regist er. this register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. the jtag programming instruction set is shown in table 25-16 . the state sequence when shifting in the programming commands is illustrated in figure 25-12 . figure 25-11. programming command register tdi tdo s t r o b e s a d d r e s s / d a t a flash eeprom fuses lock bits table 25-16. jtag programming instruction set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxx o x_xxxxxxxx (4) 2a. enter flash write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 2c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2d. load data low byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2e. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2f. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3)
356 7682c?auto?04/08 at90can32/64/128 2g. write flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 2h. poll for page write complete 0110111_00000000 xxxxx o x_xxxxxxxx (4) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 3c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 3d. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo low byte high byte 4a. enter eeprom write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 4c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 4f. write eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 4g. poll for page write complete 0110011_00000000 xxxxx o x_xxxxxxxx (4) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (11) 5c. load address low byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data low byte (8) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (5) 6c. write fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 6d. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (4) 6e. load data low byte (9) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (5) table 25-16. jtag programming instruction (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes
357 7682c?auto?04/08 at90can32/64/128 6f. write fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 6g. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (4) 6h. load data low byte (9) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (5) 6i. write fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 6j. poll for fuse write complete 0110011_00000000 xxxxx o x_xxxxxxxx (4) 7a. enter lock bit write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (11) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (6) 7c. write lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (3) 7d. poll for lock bit write complete 0110011_00000000 xxxxx o x_xxxxxxxx (4) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (8) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8c. read fuse high byte (9) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8d. read fuse low byte (10) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8e. read lock bits (11) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (7) 8f. read fuses and lock bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (7) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx table 25-16. jtag programming instruction (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes
358 7682c?auto?04/08 at90can32/64/128 notes: 1. address bits exceeding pcmsb and eeamsb ( table 25-11 and table 25-12 ) are don?t care. 2. all tdi and tdo sequences are represented by bina ry digits (0b...). 3. this command sequence is not required if the seve n msb are correctly set by the previous command seq uence (which is normally the case). 4. repeat until o = ?1?. 5. set bits to ?0? to program the corresponding fuse , ?1? to unprogram the fuse. 6. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 7. ?0? = programmed, ?1? = unprogrammed. 8. the bit mapping for fuses extended byte is listed in table 25-3 on page 336 . 9. the bit mapping for fuses high byte is listed in table 25-4 on page 336 . 10. the bit mapping for fuses low byte is listed in table 25-5 on page 337 . 11. the bit mapping for lock bits byte is listed in table 25-1 on page 335 . 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 25-16. jtag programming instruction (continued) set a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence (1)(2) tdo sequence (1)(2) notes
359 7682c?auto?04/08 at90can32/64/128 figure 25-12. state machine sequence for changing/reading the dat a word 25.9.2.4 flash data byte register the flash data byte register provides an efficient way to load the entire flash page buffer before executing page write, or to read out/verify the content of the flash. a state machine sets up the control signals to the flash and senses the strobe signals from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually consists of t he 8-bit scan chain and a 8-bit temporary reg- ister. during page load, the update-dr state copies the content of the scan chain over to the temporary register and initiates a write sequence t hat within 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates between writing the low and the high byte for each new upda te-dr state, starting with the low byte for the first update-dr encountered after entering the prog _pageload command. the program counter is pre-incremented before writing the low b yte, except for the first written byte. this ensures that the first data is written to the addre ss set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr autom atically alternates between reading the low and the high byte for each new capture-dr state , starting with the low byte for the first cap- test-logic-reset run-test/idle shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-dr scan capture-dr 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1
360 7682c?auto?04/08 at90can32/64/128 ture-dr encountered after entering the prog_pagerea d command. the program counter is post-incremented after reading each high byte, incl uding the first read byte. this ensures that the first data is captured from the first address s et up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. figure 25-13. flash data byte register the state machine controlling the flash data byte r egister is clocked by tck. during normal operation in which eight bits are shifted for each flash byte, the clock cycles needed to navigate through the tap controller automatically feeds the state machine for the flash data byte regis- ter with sufficient number of clock pulses to compl ete its operation transparently for the user. however, if too few bits are shifted between each u pdate-dr state during page load, the tap controller should stay in the run-test/idle state f or some tck cycles to ensure that there are at least 11 tck cycles between each update-dr state. 25.9.3 programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 25-16 on page 355 . 25.9.3.1 entering programming mode 1. enter jtag instruction avr_reset and shift 1 in t he reset register. 2. enter instruction prog_enable and shift 0b1010_00 11_0111_0000 in the program- ming enable register. 25.9.3.2 leaving programming mode 1. enter jtag instruction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_00 00_0000_0000 in the program- ming enable register. 4. enter jtag instruction avr_reset and shift 0 in t he reset register. tdi tdo d a t a flash eeprom fuses lock bits strobes address state machine
361 7682c?auto?04/08 at90can32/64/128 25.9.3.3 performing chip erase 1. enter jtag instruction prog_commands. 2. start chip erase using programming instruction 1a . 3. poll for chip erase complete using programming in struction 1b, or wait for t wlrh_ce (refer to table 26-15 on page 381 ). 25.9.3.4 programming the flash 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load address high byte using programming instruct ion 2b. 4. load address low byte using programming instructi on 2c. 5. load data using programming instructions 2d, 2e a nd 2f. 6. repeat steps 4 and 5 for all instruction words in the page. 7. write the page using programming instruction 2g. 8. poll for flash write complete using programming i nstruction 2h, or wait for t wlrh (refer to ). 9. repeat steps 3 to 7 until all data have been prog rammed. a more efficient data transfer can be achieved usin g the prog_pageload instruction: 1. enter jtag instruction prog_commands. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instructi ons 2b and 2c. pcword (refer to table 25-11 on page 340 ) is used to address within one page and must be wr itten as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instructi on words in the page byte-by-byte, start- ing with the lsb of the first instruction in the pa ge and ending with the msb of the last instruction in the page. use update-dr to copy the contents of the flash data byte register into the flash page location and to auto-i ncrement the program counter before each new word. 6. enter jtag instruction prog_commands. 7. write the page using programming instruction 2g. 8. poll for flash write complete using programming i nstruction 2h, or wait for t wlrh (refer to table 26-15 on page 381 ). 9. repeat steps 3 to 8 until all data have been prog rammed. 25.9.3.5 reading the flash 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3 a. 3. load address using programming instructions 3b an d 3c. 4. read data using programming instruction 3d. 5. repeat steps 3 and 4 until all data have been rea d. a more efficient data transfer can be achieved usin g the prog_pageread instruction: 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3 a. 3. load the page address using programming instructi ons 3b and 3c. pcword (refer to table 25-11 on page 340 ) is used to address within one page and must be wr itten as 0.
362 7682c?auto?04/08 at90can32/64/128 4. enter jtag instruction prog_pageread. 5. read the entire page (or flash) by shifting out a ll instruction words in the page (or flash), starting with the lsb of the first instruct ion in the page (flash) and ending with the msb of the last instruction in the page (flash) . the capture-dr state both captures the data from the flash, and also auto-increments t he program counter after each word is read. note that capture-dr comes before the shif t-dr state. hence, the first byte which is shifted out contains valid data. 6. enter jtag instruction prog_commands. 7. repeat steps 3 to 6 until all data have been read . 25.9.3.6 programming the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom write using programming instruction 4a. 3. load address high byte using programming instruct ion 4b. 4. load address low byte using programming instructi on 4c. 5. load data using programming instructions 4d and 4 e. 6. repeat steps 4 and 5 for all data bytes in the pa ge. 7. write the data using programming instruction 4f. 8. poll for eeprom write complete using programming instruction 4g, or wait for t wlrh (refer to table 26-15 on page 381 ). 9. repeat steps 3 to 8 until all data have been prog rammed. note that the prog_pageload instruction can not be used when programming the eeprom. 25.9.3.7 reading the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom read using programming instruction 5a. 3. load address using programming instructions 5b an d 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been rea d. note that the prog_pageread instruction can not be used when reading the eeprom. 25.9.3.8 programming the fuses 1. enter jtag instruction prog_commands. 2. enable fuse write using programming instruction 6 a. 3. load data high byte using programming instruction s 6b. a bit value of ?0? will program the corresponding fuse, a ?1? will unprogram the fu se. 4. write fuse high byte using programming instructio n 6c. 5. poll for fuse write complete using programming in struction 6d, or wait for t wlrh (refer to table 26-15 on page 381 ). 6. load data low byte using programming instructions 6e. a ?0? will program the fuse, a ?1? will unprogram the fuse. 7. write fuse low byte using programming instruction 6f. 8. poll for fuse write complete using programming in struction 6g, or wait for t wlrh (refer to table 26-15 on page 381 ).
363 7682c?auto?04/08 at90can32/64/128 25.9.3.9 programming the lock bits 1. enter jtag instruction prog_commands. 2. enable lock bit write using programming instructi on 7a. 3. load data using programming instructions 7b. a bi t value of ?0? will program the corre- sponding lock bit, a ?1? will leave the lock bit un changed. 4. write lock bits using programming instruction 7c. 5. poll for lock bit write complete using programmin g instruction 7d, or wait for t wlrh (refer to table 26-15 on page 381 ). 25.9.3.10 reading the fuses and lock bits 1. enter jtag instruction prog_commands. 2. enable fuse/lock bit read using programming instr uction 8a. 3. to read all fuses and lock bits, use programming instruction 8f. to only read extended fuse byte, use programming in struction 8b. to only read fuse high byte, use programming instru ction 8c. to only read fuse low byte, use programming instruc tion 8d. to only read lock bits, use programming instruction 8e. 25.9.3.11 reading the signature bytes 1. enter jtag instruction prog_commands. 2. enable signature byte read using programming inst ruction 9a. 3. load address 0x00 using programming instruction 9 b. 4. read first signature byte using programming instr uction 9c. 5. repeat steps 3 and 4 with address 0x01 and addres s 0x02 to read the second and third signature bytes, respectively. 25.9.3.12 reading the calibration byte 1. enter jtag instruction prog_commands. 2. enable calibration byte read using programming in struction 10a. 3. load address 0x00 using programming instruction 1 0b. 4. read the calibration byte using programming instr uction 10c.
364 7682c?auto?04/08 at90can32/64/128 26. decoupling capacitors the operating frequency (i.e. system clock) of the processor determines in 95% of cases the value needed for microcontroller decoupling capacit ors. the hypotheses used as first evaluation for decoupl ing capacitors are: ? the operating frequency ( f op ) supplies itself the maximum peak levels of noise. the main peaks are located at f op and 2 ? f op . ? an smc capacitor connected to 2 micro-vias on a pc b has the following characteristics: ? 1.5 nh from the connection of the capacitor to the pcb, ? 1.5 nh from the capacitor intrinsic inductance. figure 26-1. capacitor description according to the operating frequency of the product , the decoupling capacitances are chosen considering the frequencies to filter, f op and 2 ? f op . the relation between frequencies to cut and decoupl ing characteristics are defined by: and where: ? l: the inductance equivalent to the global inducta nce on the vcc/gnd lines. ? c 1 & c 2 : decoupling capacitors (c 1 = 4 ? c 2 ). then, in normalized value range, the decoupling cap acitors become: these decoupling capacitors must to be implemented as close as possible to each pair of power supply pins: ? 21-22 and 52-53 for logic sub-system, ? 64-63 for analogical sub-system. nevertheless, a bulk capacitor of 10-47 f is also needed on the power distribution network of the pcb, near the power source. for further information, please refer to applicatio n notes avr040 ?emc design considerations? and avr042 ?hardware design considerations? on the atmel web site. table 26-1. decoupling capacitors vs. frequency f op , operating frequency c 1 c 2 16 mhz 33 nf 10 nf 12 mhz 56 nf 15 nf 10 mhz 82 nf 22 nf 8 mhz 120 nf 33 nf 6 mhz 220 nf 56 nf 4 mhz 560 nf 120 nf pcb capacitor 1.5 nh 0.75 nh 0.75 nh f op 1 2 lc 1 ----------------------- = 2 f op ? 1 2 lc 2 ----------------------- =
365 7682c?auto?04/08 at90can32/64/128 27. electrical characteristics (1) 27.1 absolute maximum ratings* note: 1. electrical characteristics for this product have not yet been finalized. please consider all va lues listed herein as preliminary and non-contractual. 2. maximum current per port = 30ma 3. functional corruption may occur . automotive operating temperature..............? 40 c to +125 c *notice: stresses beyond those listed under ?absolut e maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ................................ ....? 65c to +150c voltage on any pin except reset with respect to ground ............................. . ? 0.5v to v cc +0.5v voltage on reset with respect to ground.... ? 0.5v to +13.0v voltage on v cc with respect to ground............. ? 0.5v to 6.0v dc current per i/o pin ............................. .................. 40.0 ma dc current v cc and gnd pins................................ 200.0 ma injection current at v cc = 0v to 5v (2)(3) ....................5.0ma(*)
366 7682c?auto?04/08 at90can32/64/128 27.2 dc characteristics (1) t a = -40 c to +125 c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage except xtal1 and reset pins ? 0.5 0.2 vcc (2) v v il1 input low voltage xtal1 pin - external clock selected ? 0.5 0.1 vcc (2) v v il2 input low voltage reset pin ? 0.5 0.2 vcc (2) v v ih input high voltage except xtal1 and reset pins 0.6 vcc (3) vcc + 0.5 v v ih1 input high voltage xtal1 pin - external clock selected 0.7 vcc (3) vcc + 0.5 v v ih2 input high voltage reset pin 0.85 vcc (3) vcc + 0.5 v v ol output low voltage (4) (ports a, b, c, d, e, f, g) i ol = 18 ma, v cc = 5v i ol = 8 ma, v cc = 3v 0.7 0.5 v v oh output high voltage (5) (ports a, b, c, d, e, f, g) i oh = ? 18 ma, v cc = 5v i oh = ? 8 ma, v cc = 3v 4.2 2.4 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 1.0 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 1.0 a r rst reset pull-up resistor 30 100 k r pu i/o pin pull-up resistor 20 50 k i cc power supply current active mode (external clock) 8 mhz, v cc = 5v 16 ma 16 mhz, v cc = 5v 30 ma 4 mhz, v cc = 3v 5 ma 8 mhz, v cc = 3v 8 ma power supply current idle mode (external clock) 8 mhz, v cc = 5v 9 ma 16 mhz, v cc = 5v 18 ma 4 mhz, v cc = 3v 5 ma 8 mhz, v cc = 3v 7 ma power supply current power-down mode wdt enabled, v cc = 5v 350 a wdt disabled, v cc = 5v 300 a wdt enabled, v cc = 3v 200 a wdt disabled, v cc = 3v 150 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 1.0 8.0 20 mv
367 7682c?auto?04/08 at90can32/64/128 notes: 1. all dc characteristics contained in this da tasheet are based on simulation and characterizatio n of other avr microcontrol- lers manufactured in the same process technology. t hese values are preliminary values representing des ign targets, and will be updated after characterization of actual si licon. 2. ?max? means the highest value where the pin is gu aranteed to be read as low 3. ?min? means the lowest value where the pin is gua ranteed to be read as high 4. although each i/o port can sink more than the tes t conditions (20 ma at v cc = 5v, 10 ma at v cc = 3v) under steady state conditions (non-transient), the following must be o bserved: tqfp and qfn package: 1] the sum of all iol, for all ports, should not ex ceed 400 ma. 2] the sum of all iol, for ports a0 - a7, g2, c3 - c7 should not exceed 300 ma. 3] the sum of all iol, for ports c0 - c2, g0 - g1, d0 - d7, xtal2 should not exceed 150 ma. 4] the sum of all iol, for ports b0 - b7, g3 - g4, e0 - e7 should not exceed 150 ma. 5] the sum of all iol, for ports f0 - f7, should no t exceed 200 ma. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test condition. 5. although each i/o port can source more than the t est conditions (-20 ma at v cc = 5v, -10 ma at v cc = 3v) under steady state conditions (non-transient), the following mus t be observed: tqfp and qfn package: 1] the sum of all i oh , for all ports, should not exceed -400 ma. 2] the sum of all i oh , for ports a0 - a7, g2, c3 - c7 should not exceed -300 ma. 3] the sum of all i oh , for ports c0 - c2, g0 - g1, d0 - d7, xtal2 should not exceed 1-50 ma. 4] the sum of all i oh , for ports b0 - b7, g3 - g4, e0 - e7 should not ex ceed -150 ma. 5] the sum of all i oh , for ports f0 - f7, should not exceed -200 ma. if i oh exceeds the test condition, v oh may exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 27.3 external clock drive characteristics figure 27-1. external clock drive waveforms i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 ? 50 50 na t acid analog comparator propagation delay common mode vcc/2 v cc = 2.7v 170 ns v cc = 5.0v 180 ns t a = -40 c to +125 c, v cc = 2.7v to 5.5v (unless otherwise noted) (continue d) symbol parameter condition min. typ. max. units v il1 v ih1
368 7682c?auto?04/08 at90can32/64/128 27.4 maximum speed vs. v cc maximum frequency is depending on v cc . as shown in figure 27-2., the maximum frequency vs. v cc curve is linear between 1.8v < v cc < 4.5v. to calculate the maximum frequency at a given voltage in this interval, use this equation: to calculate required voltage for a given frequency , use this equation: at 3 volt, this gives: thus, when v cc = 3v, maximum frequency will be 9.33 mhz. at 8 mhz this gives: thus, a maximum frequency of 8 mhz requires v cc = 2.7v. table 27-1. external clock drive symbol parameter v cc = 2.7 - 5.5v v cc = 4.5 - 5.5v units min. max. min. max. 1/t clcl oscillator frequency 0 8 0 16 mhz t clcl clock period 125 62.5 ns t chcx high time 50 25 ns t clcx low time 50 25 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s ? t clcl change in period from one clock cycle to the next 2 2 % table 27-2. constants used to calculate maximum speed vs. v cc voltage and frequency range a b vx fy 2.7 < vcc < 4.5 or 8 < frequency < 16 8/1.8 1.8/8 2.7 8 frequency a v vx ? ( ) fy + ? = voltage b f fy ? ( ) vx + ? = frequency 8 1.8 -------- 3 2.7 ? ( ) 8 + ? 9.33 = = voltage 1.8 8 -------- 8 8 ? ( ) 2.7 + ? 2.7 = =
369 7682c?auto?04/08 at90can32/64/128 figure 27-2. maximum frequency vs. v cc , at90can32/64/128 safe operating area 4.5v 2.7v 5.5v 8 mhz 16 mhz frequency voltag
370 7682c?auto?04/08 at90can32/64/128 27.5 two-wire serial interface characteristics table 27-3 describes the requirements for devices connected t o the two-wire serial bus. the at90can32/64/128 two-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 27-3 . notes: 1. in at90can32/64/128, this parameter is char acterized and not 100% tested. table 27-3. two-wire serial bus requirements symbol parameter condition min max units vil input low-voltage ? 0.5 0.3 vcc v vih input high-voltage 0.7 vcc vcc + 0.5 v vhys (1) hysteresis of schmitt trigger inputs 0.05 vcc (2) ? v vol (1) output low-voltage 3 ma sink current 0 0.4 v tr (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns tof (1) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf (3) 20 + 0.1c b (3)(2) 250 ns tsp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1 v cc < v i < 0.9 v cc ? 10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100 khz f scl > 100 khz t hd;sta hold time (repeated) start condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t low low period of the scl clock f scl 100 khz (6) 4.7 ? s f scl > 100 khz (7) 1.3 ? s t high high period of the scl clock f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl 100 khz 4.7 ? s f scl > 100 khz 0.6 ? s t hd;dat data hold time f scl 100 khz 0 3.45 s f scl > 100 khz 0 0.9 s t su;dat data setup time f scl 100 khz 250 ? ns f scl > 100 khz 100 ? ns t su;sto setup time for stop condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t buf bus free time between a stop and start condition f scl 100 khz 4.7 ? s v cc 0,4v ? 3ma ---------------------------- 1000ns c b ------------------- v cc 0,4v ? 3ma ---------------------------- 300ns c b ----------------
371 7682c?auto?04/08 at90can32/64/128 2. required only for f scl > 100 khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all at90can32/64/128 two-wire serial interface operation. other devices connected to the two-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the at90can32/ 64/128 two-wire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6 mhz for the low time requirement to be strictly met at f scl = 100 khz. 7. the actual low period generated by the at90can32/ 64/128 two-wire serial interface is (1/f scl - 2/f ck ), thus the low time requirement will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, at90can32/64/128 devices connected to the bus may communicate at full speed (400 khz) with ot her at90can32/64/128 devices, as well as any other device with a proper t low acceptance margin. figure 27-3. two-wire serial bus timing 27.6 spi timing characteristics see figure 27-4 and figure 27-5 for details. t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r table 27-4. spi timing parameters description mode min. typ. max. 1 sck period master see table 16-4 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1.6 s
372 7682c?auto?04/08 at90can32/64/128 note: in spi programming mode the minimum sck high/l ow period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck >12 mhz figure 27-4. spi interface timing requirements (master mode) figure 27-5. spi interface timing requirements (slave mode) 13 setup slave 10 ns 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 2 ? t ck table 27-4. spi timing parameters (continued) description mode min. typ. max. mo si (data output) sck (cpol = 1) miso (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 6 1 2 2 3 4 5 8 7 miso (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 18
373 7682c?auto?04/08 at90can32/64/128 27.7 can physical layer characteristics only pads dedicated to the can communication belong to the physical layer. notes: 1. from design simulations. 2. metastable immunity flip-flop. table : can physical layer characteristics (1) parameter condition min. max. units 1 txcan output delay vcc=2.7 v load=20 pf v ol /v oh =v cc / 2 9 ns vcc=4.5 v load=20 pf v ol /v oh =v cc / 2 5.3 2 rxcan input delay vcc=2.7 v v il /v ih =v cc / 2 9 + 1 / f clk io (2) vcc=4.5 v v il /v ih =v cc / 2 7.2 + 1 / f clk io (2)
374 7682c?auto?04/08 at90can32/64/128 27.8 adc characteristics( (1) notes: 1. all dc characteristics contained in this da tasheet are based on simulation and characterizatio n of other avr microcontrol- lers manufactured in the same process technology. t hese values are preliminary values representing des ign targets, and will be updated after characterization of actual si licon. 2. values are guidelines only. 3. minimum for av cc is 2.7 v. 4. maximum for av cc is 5.5 v table 27-5. adc characteristics, single ended channels symbol parameter condition min (2) typ (2) max (2) units resolution single ended conversion 10 bits absolute accuracy (included inl, dnl, quantization error, gain and offset error) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 1.5 3 lsb single ended conversion v ref = 4v, vcc = 4v 3 lsb single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz noise reduction mode 1.5 3 lsb single ended conversion v ref = 4v, vcc = 4v noise reduction mode 3 lsb integral non-linearity (inl) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 0.6 1.5 lsb differential non-linearity (dnl) single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz 0.3 1.5 lsb gain error single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz ? 3 0 + 3 lsb offset error single ended conversion v ref = 4v, vcc = 4v adc clock = 200 khz ? 2.5 1 + 2.5 lsb clock frequency free running conversion 50 1000 khz conversion time free running conversion 65 260 s av cc analog supply voltage v cc ? 0.3 (3) v cc + 0.3 (4) v v ref external reference voltage 2.0 av cc v v in input voltage gnd v ref v input bandwidth 38.5 khz v int internal voltage reference 2.4 2.56 2.7 v r ref reference input resistance 24 32 40 k r ain analog input resistance 100 m
375 7682c?auto?04/08 at90can32/64/128 notes: 1. all dc characteristics contained in this da tasheet are based on simulation and characterizatio n of other avr microcontrol- lers manufactured in the same process technology. t hese values are preliminary values representing des ign targets, and will be updated after characterization of actual si licon. 2. values are guidelines only. 3. minimum for av cc is 2.7 v. 4. maximum for av cc is 5.5 v table 27-6. adc characteristics, differential channels (1) symbol parameter condition min (2) typ (2) max (2) units resolution differential conversion gain = 1x or 10x 8 bits differential conversion gain = 200x 7 bits absolute accuracy gain = 1x, or 10x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz 1 4 lsb gain = 200x (7 bits) v ref = 4v, vcc = 5v adc clock = 50 - 200 khz 3 integral non-linearity (inl) (accuracy after calibration for offset and gain error) gain = 1x, 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz 0.5 3 lsb differential non-linearity (dnl) 0.4 3 lsb gain error gain = 1x, 10x or 200x ? 4 0 + 4 lsb offset error gain = 1x, 10x or 200x v ref = 4v, vcc = 5v adc clock = 50 - 200 khz ? 3 0 + 3 lsb clock frequency free running conversion 50 200 khz conversion time free running conversion 65 260 s av cc analog supply voltage v cc ? 0.3 (3) v cc + 0.3 (4) v v ref external reference voltage differential conversion 2. 0 av cc - 0.5 v v in input voltage differential conversion 0 av cc v v diff input differential voltage ?v ref /gain +v ref /gain v adc conversion output ?511 511 lsb input bandwidth differential conversion 4 khz v int internal voltage reference 2.4 2.56 2.7 v r ref reference input resistance 24 32 40 k r ain analog input resistance 100 m
376 7682c?auto?04/08 at90can32/64/128 27.9 external data memory characteristics (1) notes: 1. all dc characteristics contained in this da tasheet are based on simulation and characterizatio n of other avr microcontrol- lers manufactured in the same process technology. t hese values are preliminary values representing des ign targets, and will be updated after characterization of actual si licon. 2. this assumes 50% clock duty cycle. the half perio d is actually the high time of the external clock, xtal1. 3. this assumes 50% clock duty cycle. the half perio d is actually the low time of the external clock, x tal1. table 27-7. external data memory characteristics, v cc = 4.5 - 5.5 volts, no wait-state symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 16 mhz 1 t lhll ale pulse width 115 1.0 t clcl ? 10 ns 2 t avll address valid a to ale low 57.5 0.5 t clcl ? 5 (2) ns 3a t llax_st address hold after ale low, write access 5 5 ns 3b t llax_ld address hold after ale low, read access 5 5 ns 4 t avllc address valid c to ale low 57.5 0.5 t clcl ? 5 (2) ns 5 t avrl address valid to rd low 115 1.0 t clcl ? 10 ns 6 t avwl address valid to wr low 115 1.0 t clcl ? 10 ns 7 t llwl ale low to wr low 47.5 67.5 0.5 t clcl ? 15 (3) 0.5 t clcl + 5 (3) ns 8 t llrl ale low to rd low 47.5 67.5 0.5 t clcl ? 15 (3) 0.5 t clcl + 5 (3) ns 9 t dvrh data setup to rd high 40 40 ns 10 t rldv read low to data valid 75 1.0 t clcl ? 50 ns 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 115 1.0 t clcl ? 10 ns 13 t dvwl data setup to wr low 42.5 0.5 t clcl ? 20 (2) ns 14 t whdx data hold after wr high 115 1.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 125 1.0 t clcl ns 16 t wlwh wr pulse width 115 1.0 t clcl ? 10 ns table 27-8. external data memory characteristics, v cc = 4.5 - 5.5 volts, 1 cycle wait-state (1) symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 2.0 t clcl ? 50 ns 12 t rlrh rd pulse width 240 2.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 240 2.0 t clcl ns 16 t wlwh wr pulse width 240 2.0 t clcl ? 10 ns
377 7682c?auto?04/08 at90can32/64/128 table 27-9. external data memory characteristics, v cc = 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 0 (1) symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 325 3.0 t clcl ? 50 ns 12 t rlrh rd pulse width 365 3.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 375 3.0 t clcl ns 16 t wlwh wr pulse width 365 3.0 t clcl ? 10 ns table 27-10. external data memory characteristics, v cc = 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 1 (1) symbol parameter 8 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read low to data valid 200 3.0 t clcl ? 50 ns 12 t rlrh rd pulse width 365 3.0 t clcl ? 10 ns 14 t whdx data hold after wr high 240 2.0 t clcl ? 10 ns 15 t dvwh data valid to wr high 375 3.0 t clcl ns 16 t wlwh wr pulse width 365 3.0 t clcl ? 10 ns table 27-11. external data memory characteristics, v cc = 2.7 - 5.5 volts, no wait-state (1) symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 16 mhz 1 t lhll ale pulse width 235 t clcl ? 15 ns 2 t avll address valid a to ale low 115 0.5 t clcl ? 10 (2) ns 3a t llax_st address hold after ale low, write access 5 5 ns 3b t llax_ld address hold after ale low, read access 5 5 ns 4 t avllc address valid c to ale low 115 0.5 t clcl ? 10 (2) ns 5 t avrl address valid to rd low 235 1.0 t clcl ? 15 ns 6 t avwl address valid to wr low 235 1.0 t clcl ? 15 ns 7 t llwl ale low to wr low 115 130 0.5 t clcl ? 10 (3) 0.5 t clcl + 5 (3) ns 8 t llrl ale low to rd low 115 130 0.5 t clcl ? 10 (3) 0.5 t clcl + 5 (3) ns 9 t dvrh data setup to rd high 45 45 ns 10 t rldv read low to data valid 190 1.0 t clcl ? 60 ns
378 7682c?auto?04/08 at90can32/64/128 notes: 1. all dc characteristics contained in this da tasheet are based on simulation and characterizatio n of other avr microcontrol- lers manufactured in the same process technology. t hese values are preliminary values representing des ign targets, and will be updated after characterization of actual si licon. 2. this assumes 50% clock duty cycle. the half perio d is actually the high time of the external clock, xtal1. 3. this assumes 50% clock duty cycle. the half perio d is actually the low time of the external clock, x tal1. 11 t rhdx data hold after rd high 0 0 ns 12 t rlrh rd pulse width 235 1.0 t clcl ? 15 ns 13 t dvwl data setup to wr low 105 0.5 t clcl ? 20 (2) ns 14 t whdx data hold after wr high 235 1.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 250 1.0 t clcl ns 16 t wlwh wr pulse width 235 1.0 t clcl ? 15 ns table 27-11. external data memory characteristics, v cc = 2.7 - 5.5 volts, no wait-state (continued) (1) symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. table 27-12. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 0, srwn0 = 1 (1) symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 440 2.0 t clcl ? 60 ns 12 t rlrh rd pulse width 485 2.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 500 2.0 t clcl ns 16 t wlwh wr pulse width 485 2.0 t clcl ? 15 ns table 27-13. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 0 (1) symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0 t clcl ? 60 ns 12 t rlrh rd pulse width 735 3.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 750 3.0 t clcl ns 16 t wlwh wr pulse width 735 3.0 t clcl ? 15 ns
379 7682c?auto?04/08 at90can32/64/128 notes: 1. all dc characteristics contained in this da tasheet are based on simulation and characterizatio n of other avr microcontrol- lers manufactured in the same process technology. t hese values are preliminary values representing des ign targets, and will be updated after characterization of actual si licon. figure 27-6. external memory timing (srwn1 = 0, srwn0 = 0) table 27-14. external data memory characteristics, v cc = 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 1 (1) symbol parameter 4 mhz oscillator variable oscillator unit min. max. min. max. 0 1/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read low to data valid 690 3.0 t clcl ? 60 ns 12 t rlrh rd pulse width 735 3.0 t clcl ? 15 ns 14 t whdx data hold after wr high 485 2.0 t clcl ? 15 ns 15 t dvwh data valid to wr high 750 3.0 t clcl ns 16 t wlwh wr pulse width 735 3.0 t clcl ? 15 ns ale t1 t2 t3 write read wr t4 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9
380 7682c?auto?04/08 at90can32/64/128 figure 27-7. external memory timing (srwn1 = 0, srwn0 = 1) figure 27-8. external memory timing (srwn1 = 1, srwn0 = 0) ale t1 t2 t3 write read wr t5 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 ale t1 t2 t3 write read wr t6 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5
381 7682c?auto?04/08 at90can32/64/128 figure 27-9. external memory timing (srwn1 = 1, srwn0 = 1) (1) note: 1. the ale pulse in the last period (t4-t7) is only present if the next instruction accesses the ram (internal or external). 27.10 parallel programming characteristics figure 27-10. parallel programming timing, including some general timing requirements ale t1 t2 t3 write read wr t7 a15:8 address prev. addr. da7:0 address data prev. data xx rd da7:0 (xmbk = 0) data address system clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 13 10 11 14 15 9 t4 t5 t6 data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wl wh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl
382 7682c?auto?04/08 at90can32/64/128 figure 27-11. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 27-10 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 27-12. parallel programming timing, reading sequence (with in the same page) with timing requirements (1) xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz
383 7682c?auto?04/08 at90can32/64/128 note: 1. the timing requirements shown in figure 27-10 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. notes: 1. all dc characteristics contained in this da tasheet are based on simulation and characteriza- tion of other avr microcontrollers manufactured in the same process technology. these values are preliminary values representing design t argets, and will be updated after character- ization of actual silicon. 2. t wlrh is valid for the write flash, write eeprom, write f use bits and write lock bits commands. 3. t wlrh_ce is valid for the chip erase command. table 27-15. parallel programming characteristics, v cc = 5v 10% (1) symbol parameter min. typ. max. units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (2) 3.7 5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (3) 7.5 10 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns
384 7682c?auto?04/08 at90can32/64/128 28. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved (0xfe) reserved (0xfd) reserved (0xfc) reserved (0xfb) reserved (0xfa) canmsg msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 page 265 (0xf9) canstmh timstm15 timstm14 timstm13 timstm12 timstm11 timstm10 tim stm9 timstm8 page 264 (0xf8) canstml timstm7 timstm6 timstm5 timstm4 timstm3 timstm2 timstm1 ti mstm0 page 264 (0xf7) canidm1 idmsk 28 idmsk 27 idmsk 26 idmsk 25 idmsk 24 idmsk 23 idmsk 22 idmsk 21 page 263 (0xf6) canidm2 idmsk 20 idmsk 19 idmsk 18 idmsk 17 idmsk 16 idmsk 15 idmsk 14 idmsk 13 page 263 (0xf5) canidm3 idmsk 12 idmsk 11 idmsk 10 idmsk 9 idmsk 8 idmsk 7 idmsk 6 idmsk 5 page 263 (0xf4) canidm4 idmsk 4 idmsk 3 idmsk 2 idmsk 1 idmsk 0 rtrmsk ? idemsk page 263 (0xf3) canidt1 idt 28 idt 27 idt 26 idt 25 idt 24 idt 23 idt 22 idt 21 page 262 (0xf2) canidt2 idt 20 idt 19 idt 18 idt 17 idt 16 idt 15 idt 14 idt 13 page 262 (0xf1) canidt3 idt 12 idt 11 idt 10 idt 9 idt 8 idt 7 idt 6 idt 5 page 262 (0xf0) canidt4 idt 4 idt 3 idt 2 idt 1 idt 0 rtrtag rb1tag rb0tag page 262 (0xef) cancdmob conmob1 conmob0 rplv ide dlc3 dlc2 dlc1 dlc0 page 261 (0xee) canstmob dlcw txok rxok berr serr cerr ferr aerr page 260 (0xed) canpage mobnb3 mobnb2 mobnb1 mobnb0 ainc indx2 indx1 indx0 page 259 (0xec) canhpmob hpmob3 hpmob2 hpmob1 hpmob0 cgp3 cgp 2 cgp 1 cgp 0 page 259 (0xeb) canrec rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 page 259 (0xea) cantec tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 page 259 (0xe9) canttch timttc15 timttc14 timttc13 timttc12 timttc11 timttc10 tim ttc9 timttc8 page 258 (0xe8) canttcl timttc7 timttc6 timttc5 timttc4 timttc3 timttc2 timttc1 ti mttc0 page 258 (0xe7) cantimh cantim15 cantim14 cantim13 cantim12 cantim11 cantim10 can tim9 cantim8 page 258 (0xe6) cantiml cantim7 cantim6 cantim5 cantim4 cantim3 cantim2 cantim1 ca ntim0 page 258 (0xe5) cantcon tprsc7 tprsc6 tprsc5 tprsc4 tprsc3 tprsc2 trpsc1 tprsc0 page 258 (0xe4) canbt3 ? phs22 phs21 phs20 phs12 phs11 phs10 smp page 257 (0xe3) canbt2 ? sjw1 sjw0 ? prs2 prs1 prs0 ? page 257 (0xe2) canbt1 ? brp5 brp4 brp3 brp2 brp1 brp0 ? page 256 (0xe1) cansit1 ? sit14 sit13 sit12 sit11 sit10 sit9 sit8 page 256 (0xe0) cansit2 sit7 sit6 sit5 sit4 sit3 sit2 sit1 sit0 page 256 (0xdf) canie1 ? iemob14 iemob13 iemob12 iemob11 iemob10 iemob9 iemob8 page 255 (0xde) canie2 iemob7 iemob6 iemob5 iemob4 iemob3 iemob2 iemob1 iemob0 page 255 (0xdd) canen1 ? enmob14 enmob13 enmob12 enmob11 enmob10 enmob9 enmob8 page 255 (0xdc) canen2 enmob7 enmob6 enmob5 enmob4 enmob3 enmob2 enmob1 enmob0 page 255 (0xdb) cangie enit enboff enrx entx enerr enbx energ enovrt page 254 (0xda) cangit canit boffit ovrtim bxok serg cerg ferg aerg page 253 (0xd9) cangsta ? ovrg ? txbsy rxbsy enfg boff errp page 252 (0xd8) cangcon abrq ovrq ttc synttc listen test ena/stb swres page 251 (0xd7) reserved (0xd6) reserved (0xd5) reserved (0xd4) reserved (0xd3) reserved (0xd2) reserved (0xd1) reserved (0xd0) reserved (0xcf) reserved (0xce) udr1 udr17 udr16 udr15 udr14 udr13 udr12 udr11 udr10 page 194 (0xcd) ubrr1h ? ? ? ? ubrr111 ubrr110 ubrr19 ubrr18 page 198 (0xcc) ubrr1l ubrr17 ubrr16 ubrr15 ubrr14 ubrr13 ubrr12 ubrr11 ubrr10 page 198 (0xcb) reserved (0xca) ucsr1c ? umsel1 upm11 upm10 usbs1 ucsz11 ucsz10 ucpol1 page 197 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 page 196 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 page 194 (0xc7) reserved (0xc6) udr0 udr07 udr06 udr05 udr04 udr03 udr02 udr01 udr00 page 194 (0xc5) ubrr0h ? ? ? ? ubrr011 ubrr010 ubrr09 ubrr08 page 198 (0xc4) ubrr0l ubrr07 ubrr06 ubrr05 ubrr04 ubrr03 ubrr02 ubrr01 ubrr00 page 198 (0xc3) reserved (0xc2) ucsr0c ? umsel0 upm01 upm00 usbs0 ucsz01 ucsz00 ucpol0 page 196 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 page 195 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 page 194 (0xbf) reserved
385 7682c?auto?04/08 at90can32/64/128 (0xbe) reserved (0xbd) reserved (0xbc) twcr twint twea twsta twsto twwc twen ? twie page 211 (0xbb) twdr twdr7 twdr6 twdr5 twdr4 twdr3 twdr2 twdr1 twdr0 page 213 (0xba) twar twar6 twar5 twar4 twar3 twar2 twar1 twar0 twgce page 213 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 page 212 (0xb8) twbr twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 page 211 (0xb7) reserved (0xb6) assr ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub page 159 (0xb5) reserved (0xb4) reserved (0xb3) ocr2a ocr2a7 ocr2a6 ocr2a5 ocr2a4 ocr2a3 ocr2a2 ocr2a1 ocr2a0 page 158 (0xb2) tcnt2 tcnt27 tcnt26 tcnt25 tcnt24 tcnt23 tcnt22 tcnt21 tcnt20 page 158 (0xb1) reserved (0xb0) tccr2a foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 page 163 (0xaf) reserved (0xae) reserved (0xad) reserved (0xac) reserved (0xab) reserved (0xaa) reserved (0xa9) reserved (0xa8) reserved (0xa7) reserved (0xa6) reserved (0xa5) reserved (0xa4) reserved (0xa3) reserved (0xa2) reserved (0xa1) reserved (0xa0) reserved (0x9f) reserved (0x9e) reserved (0x9d) ocr3ch ocr3c15 ocr3c14 ocr3c13 ocr3c12 ocr3c11 ocr3c10 ocr3c9 ocr 3c8 page 141 (0x9c) ocr3cl ocr3c7 ocr3c6 ocr3c5 ocr3c4 ocr3c3 ocr3c2 ocr3c1 ocr3c0 page 141 (0x9b) ocr3bh ocr3b15 ocr3b14 ocr3b13 ocr3b12 ocr3b11 ocr3b10 ocr3b9 ocr 3b8 page 141 (0x9a) ocr3bl ocr3b7 ocr3b6 ocr3b5 ocr3b4 ocr3b3 ocr3b2 ocr3b1 ocr3b0 page 141 (0x99) ocr3ah ocr3a15 ocr3a14 ocr3a13 ocr3a12 ocr3a11 ocr3a10 ocr3a9 ocr 3a8 page 141 (0x98) ocr3al ocr3a7 ocr3a6 ocr3a5 ocr3a4 ocr3a3 ocr3a2 ocr3a1 ocr3a0 page 141 (0x97) icr3h icr315 icr314 icr313 icr312 icr311 icr310 icr39 icr38 page 142 (0x96) icr3l icr37 icr36 icr35 icr34 icr33 icr32 icr31 icr30 page 142 (0x95) tcnt3h tcnt315 tcnt314 tcnt313 tcnt312 tcnt311 tcnt310 tcnt39 tcn t38 page 140 (0x94) tcnt3l tcnt37 tcnt36 tcnt35 tcnt34 tcnt33 tcnt32 tcnt31 tcnt30 page 140 (0x93) reserved (0x92) tccr3c foc3a foc3b foc3c ? ? ? ? page 140 (0x91) tccr3b icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 page 138 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 page 135 (0x8f) reserved (0x8e) reserved (0x8d) ocr1ch ocr1c15 ocr1c14 ocr1c13 ocr1c12 ocr1c11 ocr1c10 ocr1c9 ocr 1c8 page 141 (0x8c) ocr1cl ocr1c7 ocr1c6 ocr1c5 ocr1c4 ocr1c3 ocr1c2 ocr1c1 ocr1c0 page 141 (0x8b) ocr1bh ocr1b15 ocr1b14 ocr1b13 ocr1b12 ocr1b11 ocr1b10 ocr1b9 ocr 1b8 page 141 (0x8a) ocr1bl ocr1b7 ocr1b6 ocr1b5 ocr1b4 ocr1b3 ocr1b2 ocr1b1 ocr1b0 page 141 (0x89) ocr1ah ocr1a15 ocr1a14 ocr1a13 ocr1a12 ocr1a11 ocr1a10 ocr1a9 ocr 1a8 page 141 (0x88) ocr1al ocr1a7 ocr1a6 ocr1a5 ocr1a4 ocr1a3 ocr1a2 ocr1a1 ocr1a0 page 141 (0x87) icr1h icr115 icr114 icr113 icr112 icr111 icr110 icr19 icr18 page 142 (0x86) icr1l icr17 icr16 icr15 icr14 icr13 icr12 icr11 icr10 page 142 (0x85) tcnt1h tcnt115 tcnt114 tcnt113 tcnt112 tcnt111 tcnt110 tcnt19 tcn t18 page 140 (0x84) tcnt1l tcnt17 tcnt16 tcnt15 tcnt14 tcnt13 tcnt12 tcnt11 tcnt10 page 140 (0x83) reserved (0x82) tccr1c foc1a foc1b foc1c ? ? ? ? ? page 139 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 page 138 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 page 135 (0x7f) didr1 ? ? ? ? ? ? ain1d ain0d page 271 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d page 291 (0x7d) reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
386 7682c?auto?04/08 at90can32/64/128 (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 page 286 (0x7b) adcsrb ? acme ? ? ? adts2 adts1 adts0 page 290 , 268 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 page 288 (0x79) adch - / adc9 - / adc8 - / adc7 - / adc6 - / adc5 - / adc4 adc 9 / adc3 adc8 / adc2 page 289 (0x78) adcl adc7 / adc1 adc6 / adc0 adc5 / - adc4 / - adc3 / - adc2 / - adc1 / - adc0 / page 289 (0x77) reserved (0x76) reserved (0x75) xmcrb xmbk ? ? ? ? xmm2 xmm1 xmm0 page 33 (0x74) xmcra sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 page 32 (0x73) reserved (0x72) reserved (0x71) timsk3 ? ? icie3 ? ocie3c ocie3b ocie3a toie3 page 142 (0x70) timsk2 ? ? ? ? ? ? ocie2a toie2 page 161 (0x6f) timsk1 ? ? icie1 ? ocie1c ocie1b ocie1a toie1 page 142 (0x6e) timsk0 ? ? ? ? ? ? ocie0a toie0 page 112 (0x6d) reserved (0x6c) reserved (0x6b) reserved (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 page 94 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 page 93 (0x68) reserved (0x67) reserved (0x66) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 page 42 (0x65) reserved (0x64) reserved (0x63) reserved (0x62) reserved (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 page 44 (0x60) wdtcr ? ? ? wdce wde wdp2 wdp1 wdp0 page 57 0x3f (0x5f) sreg i t h s v n z c page 11 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 page 14 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 14 0x3c (0x5c) reserved 0x3b (0x5b) rampz (1) ? ? ? ? ? ? ? rampz0 page 13 0x3a (0x5a) reserved 0x39 (0x59) reserved 0x38 (0x58) reserved 0x37 (0x57) spmcsr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen page 325 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr jtd ? ? pud ? ? ivsel ivce page 64 , 73 , 303 0x34 (0x54) mcusr ? ? ? jtrf wdrf borf extrf porf page 55 , 303 0x33 (0x53) smcr ? ? ? ? sm2 sm1 sm0 se page 46 0x32 (0x52) reserved 0x31 (0x51) ocdr idrd/ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 page 298 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 page 269 0x2f (0x4f) reserved 0x2e (0x4e) spdr spd7 spd6 spd5 spd4 spd3 spd2 spd1 spd0 page 174 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x page 174 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 page 172 0x2b (0x4b) gpior2 gpior27 gpior26 gpior25 gpior24 gpior23 gpior22 gpior21 gp ior20 page 36 0x2a (0x4a) gpior1 gpior17 gpior16 gpior15 gpior14 gpior13 gpior12 gpior11 gp ior10 page 36 0x29 (0x49) reserved 0x28 (0x48) reserved 0x27 (0x47) ocr0a ocr0a7 ocr0a6 ocr0a5 ocr0a4 ocr0a3 ocr0a2 ocr0a1 ocr0a0 page 112 0x26 (0x46) tcnt0 tcnt07 tcnt06 tcnt05 tcnt04 tcnt03 tcnt02 tcnt01 tcnt00 page 111 0x25 (0x45) reserved 0x24 (0x44) tccr0a foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 page 109 0x23 (0x43) gtccr tsm ? ? ? ? ? psr2 psr310 page 98 , 163 0x22 (0x42) eearh (2) ? ? ? ? eear11 eear10 eear9 eear8 page 22 0x21 (0x41) eearl eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 page 22 0x20 (0x40) eedr eedr7 eedr6 eedr5 eedr4 eedr3 eedr2 eedr1 eedr0 page 23 0x1f (0x3f) eecr ? ? ? ? eerie eemwe eewe eere page 23 0x1e (0x3e) gpior0 gpior07 gpior06 gpior05 gpior04 gpior03 gpior02 gpior01 gp ior00 page 36 0x1d (0x3d) eimsk int7 int6 int5 int4 int3 int2 int1 int0 page 95 0x1c (0x3c) eifr intf7 intf6 intf5 intf4 intf3 intf2 intf1 intf0 page 95 0x1b (0x3b) reserved address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
387 7682c?auto?04/08 at90can32/64/128 notes: 1. address bits exceeding pcmsb ( table 25-11 on page 340 ) are don?t care. 2. address bits exceeding eeamsb ( table 25-12 on page 340 ) are don?t care. 3. for compatibility with future devices, reserved b its should be written to zero if accessed. reserved i/o memory addresses should never be written. 4. i/o registers within the address range 0x00 - 0x1 f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 5. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit , and can therefore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 t o 0x1f only. 6. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when ad dressing i/o registers as data space using ld and st instruction s, 0x20 must be added to these addresses. the at90c an32/64/128 is a complex microcontroller with more peripheral unit s than can be supported within the 64 location rese rved in opcode for the in and out instructions. for the extended i/o s pace from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1a (0x3a) reserved 0x19 (0x39) reserved 0x18 (0x38) tifr3 ? ? icf3 ? ocf3c ocf3b ocf3a tov3 page 143 0x17 (0x37) tifr2 ? ? ? ? ? ? ocf2a tov2 page 161 0x16 (0x36) tifr1 ? ? icf1 ? ocf1c ocf1b ocf1a tov1 page 143 0x15 (0x35) tifr0 ? ? ? ? ? ? ocf0a tov0 page 112 0x14 (0x34) portg ? ? ? portg4 portg3 portg2 portg1 portg0 page 92 0x13 (0x33) ddrg ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 page 92 0x12 (0x32) ping ? ? ? ping4 ping3 ping2 ping1 ping0 page 92 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 page 91 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 page 91 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 page 92 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 page 91 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 page 91 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 page 91 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 page 91 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 page 91 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 page 91 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 page 90 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 page 90 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 page 90 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 page 90 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 page 90 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 page 90 0x02 (0x22) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 page 89 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 page 90 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 page 90 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
388 7682c?auto?04/08 at90can32/64/128 29. at90can32/64/128 typical characteristics ? the following charts show typical behavior. these figures are not tested during manufacturing. all current consumption measurements are performed with all i/o pins configured as inputs and with internal pull-ups ena bled. a sine wave generator with rail-to-rail output is used as clock source. ? the power consumption in power-down mode is indepe ndent of clock selection. ? the current consumption is a function of several f actors such as: operating voltage, operating frequency, loading of i/o pins, switching rate of i /o pins, code executed and ambient temperature. the dominating factors are operating v oltage and frequency. ? the current drawn from capacitive loaded pins may be estimated (for one pin) as c l * v cc *f where c l = load capacitance, v cc = operating voltage and f = average switching freq uency of i/o pin. ? the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the or dering code indicates. ? the difference between current consumption in powe r-down mode with watchdog timer enabled and power-down mode with watchdog timer dis abled represents the differential current drawn by the watchdog timer. 29.1 active supply current figure 29-1. active supply current vs. frequency (0.1 - 1.0 mhz) active s up p ly current vs . low frequency atd_on, te mpe ra ture = 125?c 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 0.5 1 1.5 2 2.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre que nc y (mhz ) i cc (ma)
389 7682c?auto?04/08 at90can32/64/128 figure 29-2. active supply current vs. frequency (1 - 16 mhz) figure 29-3. active supply current vs. vcc (internal rc oscillat or 8 mhz) idle s up p ly current vs . frequency te mpe ra ture = 125?c 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 fre que nc y (mhz ) i cc (ma) active s up p ly current vs . v c c internal rc oscillator, 8 mhz 125 ?c 85 ?c 25 ?c -40 ?c 0 2 4 6 8 10 12 14 16 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma)
390 7682c?auto?04/08 at90can32/64/128 figure 29-4. active supply current vs. vcc (internal rc oscillat or 1 mhz) 29.2 idle supply current figure 29-5. idle supply current vs. frequency (0.1 - 1.0 mhz) - temperature = 25c active s up p ly current vs . v c c internal rc oscillator, 1 mhz 125 ?c 85 ?c 25 ?c -40 ?c 0 500 1000 1500 2000 2500 3000 3500 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) idle s up p ly current vs . low frequency te mpe ra ture = 25?c 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre que nc y (mhz ) i cc (ma)
391 7682c?auto?04/08 at90can32/64/128 figure 29-6. idle supply current vs. frequency (0.1 - 1.0 mhz) - temperature = 125c figure 29-7. dle supply current vs. frequency (1 - 16 mhz) - tem perature = 25c idle s up p ly current vs . low frequency te mpe ra ture = 125?c 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre que nc y (mhz ) i cc (ma) idle s up p ly current vs . frequency te mpe ra ture = 25?c 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 fre que nc y (mhz ) i cc (ma)
392 7682c?auto?04/08 at90can32/64/128 figure 29-8. dle supply current vs. frequency (1 - 16 mhz) - tem perature = 125c figure 29-9. idle supply current vs. vcc (internal rc oscillator 8 mhz) idle s up p ly current vs . frequency te mpe ra ture = 125?c 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 fre que nc y (mhz ) i cc (ma) idle s up p ly current vs . v c c internal rc oscillator, 8 mhz 125 ?c 85 ?c 25 ?c -40 ?c 0 2 4 6 8 10 12 14 16 18 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma)
393 7682c?auto?04/08 at90can32/64/128 figure 29-10. idle supply current vs. vcc (internal rc oscillator 1 mhz) figure 29-11. idle supply current vs. vcc (32 khz watch crystal) idle s up p ly current vs . v c c internal rc oscillator, 1 mhz 125 ?c 85 ?c 25 ?c -40 ?c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma) idle supply current vs. vcc (32 khz watch crystal) 0 10 20 30 40 50 60 2.5 3 3.5 4 4.5 5 5.5 vcc (v) icc (ua) 25c
394 7682c?auto?04/08 at90can32/64/128 29.3 power-down supply current figure 29-12. power-down supply current vs. vcc (watchdog timer d isabled) - temp. = 25c figure 29-13. power-down supply current vs. vcc (watchdog timer d isabled) - temp.= 125c p ower-down s up p ly current vs . v c c watchdog timer disabled 25 ?c 0 1 2 3 4 5 6 7 8 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) p ower-down s up p ly current vs . v c c watchdog timer disabled 125 ?c 85 ?c 25 ?c -40 ?c 0 20 40 60 80 100 120 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua)
395 7682c?auto?04/08 at90can32/64/128 figure 29-14. power-down supply current vs. vcc (watchdog timer e nabled) - temp.= 25c figure 29-15. power-down supply current vs. vcc (watchdog timer e nabled) - temp.= 125c p ower-down s up p ly current vs . v c c watchdog timer enabled 25 ?c 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) p ower-down s up p ly current vs . v c c watchdog timer enabled 125 ?c 85 ?c 25 ?c -40 ?c 0 20 40 60 80 100 120 140 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua)
396 7682c?auto?04/08 at90can32/64/128 29.4 power-save supply current figure 29-16. power-save supply current vs. vcc (watchdog timer d isabled) 29.5 pin pull-up figure 29-17. i/o pin pull-up resistor current vs. input voltage (vcc = 5v) p ower-save s up p ly current vs . v c c (watchdog timer dis abled) 125 ?c 25 ?c 0 5 10 15 20 25 30 35 40 45 50 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) i/o p in p ull-up res is tor current vs . inp ut voltage v cc =5.0v 125 ?c -40 ?c 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v op (v) i op (ua)
397 7682c?auto?04/08 at90can32/64/128 figure 29-18. i/o pin pull-up resistor current vs. input voltage (vcc = 2.7v) figure 29-19. reset pull-up resistor current vs. reset pin voltag e (vcc = 5v) i/o p in p ull-up res is tor current vs . inp ut voltage v cc =3.0v 125 ?c -40 ?c 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 v op (v) i op (ua) res et p ull-up res is tor current vs . res et p in voltag e v cc =5.0v 125 ?c -40 ?c 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v re s e t (v) i re s e t (ua)
398 7682c?auto?04/08 at90can32/64/128 figure 29-20. reset pull-up resistor current vs. reset pin voltag e (vcc = 2.7v) 29.6 pin driver strength figure 29-21. i/o pin output voltage vs. source current (vcc = 5v ) res et p ull-up res is tor current vs . res et p in voltag e v cc =2.7v 125 ?c -40 ?c 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 v re s e t (v) i re s e t (ua) i/o p in outp ut voltage vs . s ource current v cc =5.0v 125 ?c 85 ?c 25 ?c -40 ?c 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 0 2 4 6 8 10 12 14 16 18 20 i oh (ma) v oh (v)
399 7682c?auto?04/08 at90can32/64/128 figure 29-22. i/o pin output voltage vs. source current (vcc = 2. 7v) figure 29-23. i/o pin output voltage vs. sink current (vcc = 5v) i/o p in outp ut voltage vs . s ource current v cc =3.0v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 14 16 18 20 i oh (ma) v oh (v) i/o p in outp ut voltage vs . s ink current v cc =5.0v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 2 4 6 8 10 12 14 16 18 20 i ol (ma) v ol (v)
400 7682c?auto?04/08 at90can32/64/128 figure 29-24. i/o pin output voltage vs. sink current (vcc = 2.7v ) 29.7 pin thresholds and hysteresis figure 29-25. i/o input threshold voltage vs. vcc (v ih , i/o pin read as ?1?) i/o p in outp ut voltage vs . s ink current v cc =3.0v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 10 12 14 16 18 20 i ol (ma) v ol (v) i/o p in inp ut thres hold voltage vs . v c c vih, io pin read as '1' 125 ?c -40 ?c 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v)
401 7682c?auto?04/08 at90can32/64/128 figure 1. i/o input threshold voltage vs. vcc (v il , i/o pin read as ?0?) 29.8 bod thresholds and analog comparator offset figure 29-26. bod thresholds vs. temperature (bod level is 4.1v) i/o p in inp ut thres hold voltage vs . v c c vil, io pin read as '0' 125 ?c -40 ?c 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) thre s hold (v) bod thres holds vs . temp erature bod = 4.1v 1 0 3.5 3.7 3.9 4.1 4.3 4.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 te mpe ra ture (c) thre s hold (v)
402 7682c?auto?04/08 at90can32/64/128 figure 29-27. bod thresholds vs. temperature (bod level is 2.7v) figure 29-28. bandgap voltage vs. operating voltage bod thres holds vs . temp erature bod = 2.7v 1 0 2 2.2 2.4 2.6 2.8 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 te mpe ra ture (c) thre s hold (v) bandgap voltage vs . v c c 125 ?c -40 ?c 1 1.05 1.1 1.15 1.2 2.5 3 3.5 4 4.5 5 5.5 vc c (v) ba ndga p volta ge (v)
403 7682c?auto?04/08 at90can32/64/128 29.9 internal oscillator speed figure 29-29. watchdog oscillator frequency vs. operating voltage figure 29-30. calibrated 8 mhz rc oscillator frequency vs. temper ature watchdog os cillator frequency vs . op erating voltage 125 ?c 85 ?c 25 ?c -40 ?c 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (khz ) calibrated xxxmhz rc os cillator frequency vs . temp e rature 5.0 v 7.75 7.8 7.85 7.9 7.95 8 8.05 8.1 8.15 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture f rc (mhz )
404 7682c?auto?04/08 at90can32/64/128 figure 29-31. calibrated 8 mhz rc oscillator frequency vs. operat ing voltage figure 29-32. calibrated 8 mhz rc oscillator frequency vs. osccal value calibrated xxxmhz rc os cillator frequency vs . op era ting voltage 125 ?c 85 ?c 25 ?c -40 ?c 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 8.8 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz ) int rc os cillator frequency vs . os ccal value 125 ?c -40 ?c 2 4 6 8 10 12 14 16 18 0 16 32 48 64 80 96 112 128 osccal (x1) f rc (mhz )
405 7682c?auto?04/08 at90can32/64/128 29.10 current consumption of peripheral units figure 29-33. brownout detector current vs. operating voltage figure 29-34. aref external reference current vs. operating volta ge brownout detector current vs . v c c 125 ?c 85 ?c 25 ?c -40 ?c 0 5 10 15 20 25 30 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) aref current with adc at 1mhz vs . v c c 125 ?c -40 ?c 50 75 100 125 150 175 200 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua)
406 7682c?auto?04/08 at90can32/64/128 figure 29-35. analog comparator current vs. operating voltage figure 29-36. programming current vs. operating voltage analog comp arator current vs . v c c 125 ?c -40 ?c 0 20 40 60 80 100 120 140 160 180 200 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) eep rom write current vs . vcc ext clk 125 ?c 85 ?c 25 ?c -40 ?c 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ma)
407 7682c?auto?04/08 at90can32/64/128 29.11 current consumption in reset and reset pulse w idth figure 29-37. reset supply current vs. operating voltage (0.1 - 1 .0 mhz) (excluding current through the reset pull-up) figure 29-38. reset supply current vs. operating voltage (1 - 16 mhz) (excluding current through the reset pull-up) res et s up p ly current vs . v c c excluding current through the reset pullup 5.5 v 5.0 v 4.5 v 4.0 v 3.6 v 3.3 v 3.0 v 2.7 v 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 fre que nc y (mhz ) i cc (ma) res et s up p ly current vs . v c c excluding current through the reset pullup 5.5 v 5.0 v 4.5 v 4.0 v 3.6 v 3.3 v 3.0 v 2.7 v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 2 4 6 8 10 12 14 16 18 20 fre que nc y (mhz ) i cc (ma)
408 7682c?auto?04/08 at90can32/64/128 figure 29-39. minimum reset pulse width vs. operating voltage 29.12 analog to digital converter figure 29-40. integral non linearity (inl), single ended res et p uls e width vs . v c c 125 ?c 85 ?c 25 ?c -40 ?c 0 200 400 600 800 1000 1200 1400 2.5 3 3.5 4 4.5 5 5.5 v cc (v) puls e width (ns ) analog to digital converter - integral non linearit y inl single ende d, vc c = 4v, vre f = 4v 0.54 0.56 0.58 0.6 0.62 0.64 0.66 0.68 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb
409 7682c?auto?04/08 at90can32/64/128 figure 29-41. integral non linearity (inl), differential inputs figure 29-42. differential non linearity (dnl), single ended analog to digital converter - integral non linearit y inl diffe re ntia l inputs , vc c = 4v, vre f = 4v diff x1 diff x200 0 0.1 0.2 0.3 0.4 0.5 0.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb analog to digital converter - differential non line arity dnl single ende d, vc c = 4v, vre f = 4v 0.3 0.32 0.34 0.36 0.38 0.4 0.42 0.44 0.46 0.48 0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb
410 7682c?auto?04/08 at90can32/64/128 figure 29-43. differential non linearity (dnl), differential inpu ts figure 29-44. offset, single ended analog to digital converter - differential non lin earity dnl diffe re ntia l inputs , vc c = 4v, vre f = 4v diff x1 diff x200 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb analog to digital converter - offs et single ende d, vc c = 4v, vre f = 4v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb
411 7682c?auto?04/08 at90can32/64/128 figure 29-45. offset, differential inputs figure 29-46. gain, single ended analog to digital converter - offs et diffe re ntia l inputs , vc c = 4v, vre f = 4v diff x1 diff x200 0.2 0.22 0.24 0.26 0.28 0.3 0.32 0.34 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb analog to digital converter - gain single ende d, vc c = 4v, vre f = 4v -1.2 -1 -0.8 -0.6 -0.4 -0.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb
412 7682c?auto?04/08 at90can32/64/128 figure 29-47. gain, differential inputs figure 29-48. absolute accuracy (tue), single ended analog to digital converter - gain diffe re ntia l inputs , vc c = 5v, vre f = 4v diff x1 diff x200 -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb analog to digital converter - abs olute accuracy (tu e) single ende d, vc c = 4v, vre f = 4v 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb
413 7682c?auto?04/08 at90can32/64/128 figure 29-49. absolute accuracy (tue), differential inputs analog to digital converter - abs olute accuracy (tu e) diffe re ntia l inputs , vc c = 5v, vre f = 4v diff x1 diff x200 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 te mpe ra ture lsb
414 7682c?auto?04/08 at90can32/64/128 30. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigne d r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc k none 3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 call k direct subroutine call pc k none 4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0 ) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b) =0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)= 1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) t hen pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) t hen pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2
415 7682c?auto?04/08 at90can32/64/128 brie k branch if interrupt enabled if ( i = 1) then p c pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1 none 2 cbi p,b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1 c 1 clc clear carry c 0 c 1 sen set negative flag n 1 n 1 cln clear negative flag n 0 n 1 sez set zero flag z 1 z 1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1 i 1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1 s 1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1 v 1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1 t 1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1 h 1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post-inc rd (rampz:z), rampz:z rampz:z+1 none 3 spm store program memory (z) r1:r0 none - mnemonics operands description operation flags #clocks
416 7682c?auto?04/08 at90can32/64/128 in rd, p in port rd p none 1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) no ne 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
417 7682c?auto?04/08 at90can32/64/128 31. ordering information notes: 1. these devices can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering informa- tion and minimum quantities. 2. green and rohs packaging 3. tape and reel with dry-pack delivery. 4. for speed vs. v cc ,see figure 27-2 on page 369 . 32. packaging information ordering code (1) speed (mhz (4) ) power supply (v) package (2)(3) operation range at90can32-15at 16 2.7 - 5.5 a2 64 automotive (-40 to + 85c) at90can32-15at1 16 2.7 - 5.5 a2 64 automotive (-40 to +105c) at90can32-15az 16 2.7 - 5.5 a2 64 automotive (-40 to + 125c) at90can32-15mt 16 2.7 - 5.5 z64-1 automotive (-40 to + 85c) at90can32-15mt1 16 2.7 - 5.5 z64-1 automotive (-40 to +105c) at90can32-15mz 16 2.7 - 5.5 z64-1 automotive (-40 to + 125c) at90can64-15at 16 2.7 - 5.5 a2 64 automotive (-40 to + 85c) at90can64-15at1 16 2.7 - 5.5 a2 64 automotive (-40 to +105c) at90can64-15az 16 2.7 - 5.5 a2 64 automotive (-40 to + 125c) at90can64-15mt 16 2.7 - 5.5 z64-2 automotive (-40 to + 85c) at90can64-15mt1 16 2.7 - 5.5 z64-2 automotive (-40 to +105c) at90can64-15mz 16 2.7 - 5.5 z64-2 automotive (-40 to + 125c) at90can128-15at 16 2.7 - 5.5 a2 64 automotive (-40 to +85c) AT90CAN128-15AT1 16 2.7 - 5.5 a2 64 automotive (-40 to +105c) at90can128-15az 16 2.7 - 5.5 a2 64 automotive (-40 to +125c) at90can128-15mt 16 2.7 - 5.5 z64-2 automotive (-40 to +85c) at90can128-15mt1 16 2.7 - 5.5 z64-2 automotive (-40 to +105c) at90can128-15mz 16 2.7 - 5.5 z64-2 automotive (-40 to +125c) package type a2 64 64-lead, thin (1.0 mm) plastic gull wing quad flat package z64-1 64-lead, qfn, exposed d2/e2: 5.4 +/- 0.1mm z-64-2 64-lead, qfn, exposed d2/e2: 6.0 +/- 0.1mm
418 7682c?auto?04/08 at90can32/64/128 32.1 tqfp64
419 7682c?auto?04/08 at90can32/64/128 32.2 qfn64
420 7682c?auto?04/08 at90can32/64/128 33. errata 33.1 errata summary 33.1.1 at90can128 revd (date code 0107) ? can transmission after 3-bit intermission ? asynchronous timer-2 wakes up without interrupt ? spi programming timing 33.1.2 at90can32 revb (date code 0107) ? can transmission after 3-bit intermission ? asynchronous timer-2 wakes up without interrupt ? spi programming timing 33.1.3 at90can64 reva ? lpm instruction versus protection levels and boots ize ? can acknowledge error in 3-sample mode with presca ler =1 ? can transmission after 3-bit intermission ? asynchronous timer-2 wakes up without interrupt 33.2 errata description 5. lpm instruction versus protection levels and b ootsize in at90can64 product, if the bootloader and applica tion protection modes are pro- grammed at level 3, the lpm instruction does not op erate properly in some configuration cases. it will not load the right constant value. t he differents cases versus bootsize value and flash memory areas are detailed in following ta bles : let?s consider 4 sections in the flash, described b elow: failing cases : problem fix / workaround if protection level 3 is mandatory, the lpm instruc tion must be moved outside the failing sections. table 33-1. flash memory sections memory space a : application memory space b : application memory space c : application memory space d : bootloader bootsize=4096 words 0000h-2fffh 3000h-3fffh 4000h-6fff h 7000h-7fffh bootsize=2048 words 0000h-37ffh 3800h-3fffh 4000h-77ff h 7800h-7fffh bootsize=1024 words 0000h-3bffh 3c00h-3fffh 4000h-7bff h 7c00h-7fffh bootsize=512 words 0000h-3dffh 3e00h-3fffh 4000h-7dffh 7e00h-7fffh from memory space t o m e m e o r y space bug comment lpm instruction d b allowed but should not be valid lpm instruction b d allowed but should not be valid lpm instruction b a or c not allowed but should be lpm instruction a or c b not allowed but should be
421 7682c?auto?04/08 at90can32/64/128 4. can acknowledge error in 3-sample mode with presc aler =1 some acknowledge errors can occur when the clock pr escaler = 1 (brp[5..0] = 0 in canbtr1 register) and the smp bit is set (canbtr3[0 ] = 1 in canbtr3 register). that can result in a reduction of the maximum length of the can bus. problem fix / workaround if brp[5..0]=0 use smp=0. 3. can transmission after 3-bit intermission if a transmit message object (mob) is enabled while the can bus is busy with an on going message, the transmitter will wait for the 3-bit in termission before starting its transmission. this is in full agreement with the can recommendati on. if the transmitter lost arbitration against another node, two conditions can occur: - at least one receive mob of the chip are programme d to accept the incoming message. in this case, the transmitter will wait for the next 3 -bit intermission to retry its transmission. - no receive mob of the chip are programmed to accep t the incoming message. in this case the transmitter will wait for a 4-bit intermission to retry its transmission. in this case, any other can nodes ready to transmit after a 3-bit int ermission will start transmit before the chip transmitter, even if their messages have lower priority ids. problem fix / workaround always have a receive mob enabled ready to accept a ny incoming messages. thanks to the implementation of the can interface, a receive mob must be enable at latest, before the 1 st bit of the dlc field. the receive mob status regis ter is written (rxok if message ok) immediately after the 6th bit of the end of frame f ield. this will leave in can2.0a mode a minimum 19-bit time delay to respond to the end of message interrupt (rxok) and re- enable the receive mob before the start of the dlc field of the next incoming message. this minimum delay will be 39-bit time in can2.0b. see c an2.0a can2.0b frame timings below. workaround implementation the workaround is to have the last mob (mob14) as " spy" enabled all the time; it is the mob of lowest priority. if a mob other than mob14 is pr ogrammed in receive mode and its accep- tance filter matches with the incoming message id, this mob will take the message. mob14 will only take messages than no other mobs will hav e accepted. mob14 will need to be re- enabled fast enough to manage back to back frames. the deadline to do this is the begin- ning of dlc slot of incoming frames as explained ab ove. minimum code to insert in can interrupt routine: can 2.0a arbitration field control field end of frame crc field ack field inter- mission 19-bit time minimum t 1 (rxok) t 2 11-bit identifier id10..0 crc del. ack del. 15-bit crc sof sof rtr ide r0 ack 7 bits 4-bit dlc dlc4..0 3 bits can 2.0b 39-bit time minimum t 1 (rxok) t 2 end of frame crc field ack field inter- mission arbitration field control field crc del. ack del. 15-bit crc sof sof ack 7 bits 3 bits 11-bit base identifier idt28..18 18-bit identifier extension id17..0 4-bit dlc dlc4..0 srr ide r0 rtr r1
422 7682c?auto?04/08 at90can32/64/128 __interrupt void can_int_handler(void) { if ((cansit1 & 0x40) == 0x40 ) /* mob14 interrupt ( sit14=1) */ { canpage = (0x0e << 4); /* select mob14 */ canstmob = 0x00; /* reset mob14 status */ cancdmob = 0x88; /* reception enable */ } ........ ........ } 2. asynchronous timer-2 wakes up without interrupt the asynchronous timer can wake from sleep without giving interrupt. the error only occurs if the interrupt flag(s) is cleared by software les s than 4 cycles before going to sleep and this clear is done exactly when it is supposed to be set (compare match or overflow). only the interrupts flags are affected by the clear, not the signal witch is used to wake up the part. problem fix / workaround no known workaround, try to lock the code to avoid such a timing. 1. spi programming timing when the fuse high byte or the extended fuse byte h as been written, it is necessary to wait the end of the programming using ?poll rdy/bsy? ins truction. if this instruction is entered too speedily after the ?write fuse? instruction, th e fuse low byte is written instead of high fuse /extended fuse byte. problem fix / workaround wait sometime before applying the ?poll rdy/bsy? in struction. for 8mhz system clock, waiting 1 s is sufficient.
423 7682c?auto?04/08 at90can32/64/128 34. datasheet revision history for at90can32/64/128 please note that the referring page numbers in this section are referring to this document. the referring revision in this section are referrin g to the document revision. 34.1 7682a - 01/07 1. rev a. document creation. 34.2 7682b - 09/07 1. adc conversion time updated. see ?analog to digital converter - adc? on page 272 2. can filter values corrected. see ?acceptance filter? on page 244 . 34.3 7682c - 04/08 1. updated errata list. 2. updated pacakge drawings.
1 7682c?auto?04/08 at90can32/64/128 1 description ...................................... ................................................... ...... 2 1.1 comparison between at90can32, at90can64 and at90 can128 ................2 1.2 part description ............................... ................................................... ................2 1.3 disclaimer ..................................... ................................................... ...................3 1.4 automotive quality grade ....................... ................................................... .........3 1.5 block diagram .................................. ................................................... ................4 1.6 pin configurations ............................. ................................................... ...............5 1.7 pin descriptions ............................... ................................................... ................6 2 about code examples .............................. ............................................... 8 3 avr cpu core .................................................. ........................................ 9 3.1 introduction ................................... ................................................... ...................9 3.2 architectural overview ......................... ................................................... ............9 3.3 alu ? arithmetic logic unit .................... ................................................... .......10 3.4 status register ................................ ................................................... ..............11 3.5 general purpose register file .................. ................................................... .....12 3.6 stack pointer .................................. ................................................... ................14 3.7 instruction execution timing ................... ................................................... .......14 3.8 reset and interrupt handling ................... ................................................... ......15 4 memories ......................................... ................................................... .... 18 4.1 in-system reprogrammable flash program memory .. ....................................18 4.2 sram data memory ............................... ................................................... .......19 4.3 eeprom data memory ............................. ................................................... ....22 4.4 i/o memory ..................................... ................................................... ...............27 4.5 external memory interface ...................... ................................................... .......27 4.6 general purpose i/o registers .................. ................................................... ....36 5 system clock ..................................... ................................................... .. 37 5.1 clock systems and their distribution ........... ................................................... ..37 5.2 clock sources .................................. ................................................... ..............38 5.3 default clock source ........................... ................................................... ..........38 5.4 crystal oscillator ............................. ................................................... ...............39 5.5 low-frequency crystal oscillator ............... ................................................... ....40 5.6 calibrated internal rc oscillator .............. ................................................... .....41 5.7 external clock ................................. ................................................... ...............42 5.8 clock output buffer ............................ ................................................... ............43 5.9 timer/counter2 oscillator ...................... ................................................... ........43
2 7682c?auto?04/08 at90can32/64/128 5.10 system clock prescaler ........................ ................................................... .........44 6 power management and sleep modes ................. ................................ 46 6.1 idle mode ...................................... ................................................... .................47 6.2 adc noise reduction mode ....................... ................................................... ...47 6.3 power-down mode ................................ ................................................... .........47 6.4 power-save mode ................................ ................................................... ..........47 6.5 standby mode ................................... ................................................... .............48 6.6 minimizing power consumption ................... ................................................... ..48 7 system control and reset ......................... ........................................... 51 7.1 reset .......................................... ................................................... ....................51 7.2 internal voltage reference ..................... ................................................... .......56 7.3 watchdog timer ................................. ................................................... ............57 7.4 timed sequences for changing the configuration o f the watchdog timer ......59 8 interrupts ....................................... ................................................... ...... 60 8.1 interrupt vectors in at90can32/64/128 .......... ................................................60 8.2 moving interrupts between application and boot s pace ..................................64 9 i/o-ports ........................................ ................................................... ....... 66 9.1 introduction ................................... ................................................... .................66 9.2 ports as general digital i/o ................... ................................................... ........67 9.3 alternate port functions ....................... ................................................... .........71 9.4 register description for i/o-ports ............. ................................................... .....89 10 external interrupts ............................. ................................................... . 93 11 timer/counter3/1/0 prescalers ................... .......................................... 96 11.1 overview ...................................... ................................................... ..................96 11.2 timer/counter0/1/3 prescalers register descript ion ........................................98 12 8-bit timer/counter0 with pwm ................... ......................................... 99 12.1 features ...................................... ................................................... ...................99 12.2 overview ...................................... ................................................... ..................99 12.3 timer/counter clock sources ................... ................................................... ...100 12.4 counter unit .................................. ................................................... ...............100 12.5 output compare unit ........................... ................................................... ........101 12.6 compare match output unit ..................... ................................................... ...103 12.7 modes of operation ............................ ................................................... .........104 12.8 timer/counter timing diagrams ................. ................................................... .108
3 7682c?auto?04/08 at90can32/64/128 12.9 8-bit timer/counter register description ...... ..................................................1 09 13 16-bit timer/counter (timer/counter1 and timer/co unter3) ........... 113 13.1 features ...................................... ................................................... .................113 13.2 overview ...................................... ................................................... ................113 13.3 accessing 16-bit registers .................... ................................................... ......116 13.4 timer/counter clock sources ................... ................................................... ...119 13.5 counter unit .................................. ................................................... ...............120 13.6 input capture unit ............................ ................................................... ............121 13.7 output compare units .......................... ................................................... .......123 13.8 compare match output unit ..................... ................................................... ...125 13.9 modes of operation ............................ ................................................... .........126 13.10 timer/counter timing diagrams ................ ................................................... ..134 13.11 16-bit timer/counter register description .... ..................................................1 35 14 8-bit timer/counter2 with pwm and asynchronous op eration ...... 145 14.1 features ...................................... ................................................... .................145 14.2 overview ...................................... ................................................... ................145 14.3 timer/counter clock sources ................... ................................................... ...147 14.4 counter unit .................................. ................................................... ...............147 14.5 output compare unit ........................... ................................................... ........148 14.6 compare match output unit ..................... ................................................... ...149 14.7 modes of operation ............................ ................................................... .........150 14.8 timer/counter timing diagrams ................. ................................................... .154 14.9 8-bit timer/counter register description ...... ..................................................1 56 14.10 asynchronous operation of the timer/counter2 . ............................................159 14.11 timer/counter2 prescaler ..................... ................................................... .......162 15 output compare modulator - ocm .................. ................................... 164 15.1 overview ...................................... ................................................... ................164 15.2 description ................................... ................................................... ................164 16 serial peripheral interface ? spi ............... .......................................... 167 16.1 features ...................................... ................................................... .................167 16.2 ss pin functionality ................................ ................................................... .....171 16.3 data modes .................................... ................................................... ..............174 17 usart (usart0 and usart1) ....................... ................................... 176 17.1 features ...................................... ................................................... .................176
4 7682c?auto?04/08 at90can32/64/128 17.2 overview ...................................... ................................................... ................176 17.3 dual usart .................................... ................................................... ............176 17.4 clock generation .............................. ................................................... ...........178 17.5 serial frame .................................. ................................................... ..............180 17.6 usart initialization .......................... ................................................... ...........181 17.7 data transmission ? usart transmitter ......... ..............................................182 17.8 data reception ? usart receiver ............... .................................................18 5 17.9 asynchronous data reception ................... ................................................... .189 17.10 multi-processor communication mode ........... ................................................192 17.11 usart register description ................... ................................................... ....194 17.12 examples of baud rate setting ................ ................................................... ...199 18 two-wire serial interface ....................... .............................................. 203 18.1 features ...................................... ................................................... .................203 18.2 two-wire serial interface bus definition ...... ................................................... 203 18.3 data transfer and frame format ................ ................................................... 204 18.4 multi-master bus systems, arbitration and synch ronization ..........................206 18.5 overview of the twi module .................... ................................................... ....208 18.6 twi register description ...................... ................................................... .......211 18.7 using the twi ................................. ................................................... .............214 18.8 transmission modes ............................ ................................................... ........217 18.9 multi-master systems and arbitration .......... ................................................... 231 19 controller area network - can ................... ........................................ 233 19.1 features ...................................... ................................................... .................233 19.2 can protocol .................................. ................................................... .............233 19.3 can controller ................................ ................................................... .............239 19.4 can channel ................................... ................................................... ............240 19.5 message objects ............................... ................................................... ..........242 19.6 can timer ..................................... ................................................... ..............246 19.7 error management .............................. ................................................... .........246 19.8 interrupts .................................... ................................................... ..................248 19.9 can register description ...................... ................................................... ......250 19.10 general can registers ........................ ................................................... .......251 19.11 mob registers ................................ ................................................... .............260 19.12 examples of can baud rate setting ............ .................................................26 5 20 analog comparator ............................... ............................................... 268
5 7682c?auto?04/08 at90can32/64/128 20.1 overview ...................................... ................................................... ................268 20.2 analog comparator register description ........ ...............................................268 20.3 analog comparator multiplexed input ........... ..................................................2 70 21 analog to digital converter - adc ............... ....................................... 272 21.1 features ...................................... ................................................... .................272 21.2 operation ..................................... ................................................... ................273 21.3 starting a conversion ......................... ................................................... .........274 21.4 prescaling and conversion timing .............. ................................................... 275 21.5 changing channel or reference selection ....... ..............................................278 21.6 adc noise canceler ............................ ................................................... ........279 21.7 adc conversion result ......................... ................................................... ......283 21.8 adc register description ...................... ................................................... ......286 22 jtag interface and on-chip debug system ......... ............................. 292 22.1 features ...................................... ................................................... .................292 22.2 overview ...................................... ................................................... ................292 22.3 test access port ? tap ........................ ................................................... .......292 22.4 tap controller ................................ ................................................... .............295 22.5 using the boundary-scan chain ................. ................................................... .296 22.6 using the on-chip debug system ................ ................................................... 296 22.7 on-chip debug specific jtag instructions ...... ...............................................297 22.8 on-chip debug related register in i/o memory .. ..........................................298 22.9 using the jtag programming capabilities ....... .............................................298 22.10 bibliography ................................. ................................................... ................298 23 boundary-scan ieee 1149.1 (jtag) ................ ................................... 299 23.1 features ...................................... ................................................... .................299 23.2 system overview ............................... ................................................... ..........299 23.3 data registers ................................ ................................................... .............299 23.4 boundary-scan specific jtag instructions ...... ...............................................301 23.5 boundary-scan related register in i/o memory .. ..........................................303 23.6 boundary-scan chain ........................... ................................................... .......303 23.7 at90can32/64/128 boundary-scan order .......... ..........................................313 23.8 boundary-scan description language files ...... .............................................319 24 boot loader support ? read-while-write self-progr amming ......... 320 24.1 features ...................................... ................................................... .................320 24.2 application and boot loader flash sections .... ..............................................320
6 7682c?auto?04/08 at90can32/64/128 24.3 read-while-write and no read-while-write flash sections .........................320 24.4 boot loader lock bits ......................... ................................................... .........323 24.5 entering the boot loader program .............. ................................................... 324 24.6 addressing the flash during self-programming .. ...........................................326 24.7 self-programming the flash .................... ................................................... ....327 25 memory programming .............................. ........................................... 335 25.1 program and data memory lock bits ............. ................................................335 25.2 fuse bits ..................................... ................................................... .................336 25.3 signature bytes ............................... ................................................... .............338 25.4 calibration byte .............................. ................................................... ..............338 25.5 parallel programming overview ................. ................................................... .338 25.6 parallel programming .......................... ................................................... ........341 25.7 spi serial programming overview ............... ..................................................3 47 25.8 spi serial programming ........................ ................................................... ......348 25.9 jtag programming overview ..................... ................................................... 351 26 decoupling capacitors ........................... ............................................. 364 27 electrical characteristics (1) ............................................... ................................................ 365 27.1 absolute maximum ratings* ..................... ................................................... ...365 27.2 dc characteristics (1) .................................................. .....................................366 27.3 external clock drive characteristics .......... ................................................... ..367 27.4 maximum speed vs. vcc ......................... ................................................... ...368 27.5 two-wire serial interface characteristics ..... ..................................................3 70 27.6 spi timing characteristics .................... ................................................... .......371 27.7 can physical layer characteristics ............ ................................................... 373 27.8 adc characteristics( (1) .................................................. .................................374 27.9 external data memory characteristics (1) .................................................. ......376 27.10 parallel programming characteristics ......... ................................................... .381 28 register summary ................................ ............................................... 384 29 at90can32/64/128 typical characteristics ........ .............................. 388 29.1 active supply current ......................... ................................................... .........388 29.2 idle supply current ........................... ................................................... ...........390 29.3 power-down supply current ..................... ................................................... ...394 29.4 power-save supply current ..................... ................................................... ....396 29.5 pin pull-up ................................... ................................................... .................396
7 7682c?auto?04/08 at90can32/64/128 29.6 pin driver strength ........................... ................................................... ............398 29.7 pin thresholds and hysteresis ................. ................................................... ...400 29.8 bod thresholds and analog comparator offset ... .........................................401 29.9 internal oscillator speed ..................... ................................................... .........403 29.10 current consumption of peripheral units ...... .................................................40 5 29.11 current consumption in reset and reset pulse w idth ..................................407 29.12 analog to digital converter .................. ................................................... .......408 30 instruction set summary ......................... ............................................ 414 31 ordering information ............................ ............................................... 417 32 packaging information ........................... ............................................. 417 32.1 tqfp64 ........................................ ................................................... ...............418 32.2 qfn64 ......................................... ................................................... ................419 33 errata .......................................... ................................................... ........ 420 33.1 errata summary ................................ ................................................... ...........420 33.2 errata description ............................ ................................................... ............420 34 datasheet revision history for at90can32/64/128 . ........................ 423 34.1 7682a - 01/07 ................................. ................................................... .............423 34.2 7682b - 09/07 ................................. ................................................... .............423 34.3 7682c - 04/08 ................................. ................................................... .............423
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